Olivier Marcelot

Radiation Effects in Pinned Photodiode CMOS Image Sensors: Pixel Performance Degradation Due to Total Ionizing Dose

Several Pinned Photodiode (PPD) CMOS Image Sensors (CIS) are designed, manufactured, characterized and exposed biased to ionizing radiation up to 10 kGy(SiO2 ). In addition to the usually reported dark current increase and quantum efficiency drop at short wavelengths, several original radiation effects are shown: an increase of the pinning voltage, a decrease of the buried photodiode full well capacity, a large change in charge transfer efficiency, the creation of a large number of Total Ionizing Dose (TID) induced Dark Current Random Telegraph Signal (DC-RTS) centers active in the photodiode (even when the Transfer Gate (TG) is accumulated) and the complete depletion of the Pre-Metal Dielectric (PMD) interface at the highest TID leading to a large dark current and the loss of control of the TG on the dark current. The proposed mechanisms at the origin of these degradations are discussed. It is also demonstrated that biasing (i.e., operating) the PPD CIS during irradiation does not enhance the degradations compared to sensors grounded during irradiation.

Detection of Cs2Ge+ clusters for the quantification of germanium atoms by secondary ion mass spectrometry: Application to the characterization of Si1−xGex layers (0⩽x⩽1) and germanium diffusion in silicon

We have studied the matrix effects in Si1−xGex structures under O2+ and Cs+ bombardments. Matrix effects are practically suppressed with Cs2Ge+ secondary ions, for Ge concentrations between 0 and 100at.%. A procedure for the accurate quantification of the Ge concentration in Si1−xGex alloys using Cs2Ge+ and CsGe+ clusters has been proposed. For structures in which the Ge content is constant over several hundreds of nanometers, both methods provide very similar results, with an excellent agreement between the Ge concentrations measured by secondary ions mass spectrometry and x-ray diffraction. However, for continuously varying Ge concentration profiles, the nonlinear response of the CsGe+ normalized intensity and the persistence of strong matrix effects for CsSi+ ions lead to differences between the Ge concentration profiles measured with the CsGe+ method compared to the Cs2Ge+ one. The latter is therefore the only reliable method for the study of Ge indiffusion into Si from a pure Ge layer grown by chemic...

Pixel Level Characterization of Pinned Photodiode and Transfer Gate Physical Parameters in CMOS Image Sensors

A method to extract the pinned photodiode (PPD) physical parameters inside a CMOS image sensor pixel array is presented. The proposed technique is based on the Tan et al. pinning voltage characteristic. This pixel device characterization can be performed directly at the solid-state circuit output without the need of any external test structure. The presented study analyzes the different injection mechanisms involved in the different regimes of the characteristic. It is demonstrated that in addition to the pinning voltage, this fast measurement can be used to retrieve the PPD capacitance, the pixel equilibrium full well capacity, and both the transfer gate threshold voltage and its channel potential at a given gate voltage. An alternative approach is also proposed to extract an objective pinning voltage value from this measurement.

Study of CCD Transport on CMOS Imaging Technology: Comparison Between SCCD and BCCD, and Ramp Effect on the CTI

This paper presents measurements performed on charge-coupled device (CCD) structures manufactured on a deep micrometer CMOS imaging technology, in surface channel CCD and in buried channel CCD mode. The charge transfer inefficiency is evaluated for both CCD modes with regard to the injected charge, and the influence of the rising and falling time effect is explored. Controlling the ramp and especially reducing its abruptness allows to get much lower charge transfer inefficiency in buried CCD mode. On the contrary, we did not observe any effect of the ramp on surface channel CCD mode because of the presence of interface traps at the silicon-oxide interface.

Enhanced Near-Infrared Response CMOS Image Sensors Using High-Resistivity Substrate: Photodiodes Design Impact on Performances

A three-transistor pixel, front-side-illuminated CMOS image sensor is developed and realized using high-resistivity (HR) silicon (Na ≈ 1012 cm-3) to enhance its near-infrared response thanks to a large depleted depth. Both TCAD simulations and an analytical model are used to estimate the space-charge region extension of a photodiode. A strong 3-D geometrical variation with pixel design geometry is shown. Punchthrough current measurements in a pixel array are used to demonstrate these variations and their impact. The punchthrough and crosstalk measurements can provide an optimum pixel design on HR silicon. Electrooptical characterization demonstrates excellent quantum efficiency despite slightly degraded crosstalk performances for near-infrared wavelengths.

Plan View and Cross-Sectional View EBIC Measurements: Effect of e-Beam Injection Conditions on Extracted Minority Carrier Transport Properties

The application of low-doped epitaxial layers and the increase of complexity of silicon photodiode design require the knowledge of the basic physical parameters, such as minority carrier lifetime or diffusion length, to improve the photodiode performance simulation. In this paper, electron-beam-induced current technique is used to evaluate minority carrier lifetime and diffusion length on a silicon photodiode. Particular focus is to compare plan view and cross-sectional view testing geometry, and also to evaluate artefacts introduced by high injection conditions unavoidable in lifetime measurement.

Radiation Hardening of Digital Color CMOS Camera-on-a-Chip Building Blocks for Multi-MGy Total Ionizing Dose Environments

The Total Ionizing Dose (TID) hardness of digital color Camera-on-a-Chip (CoC) building blocks is explored in the Multi-MGy range using 60Co gamma-ray irradiations. The performances of the following CoC subcomponents are studied: radiation hardened (RH) pixel and photodiode designs, RH readout chain, Color Filter Arrays (CFA) and column RH Analog-to-Digital Converters (ADC). Several radiation hardness improvements are reported (on the readout chain and on dark current). CFAs and ADCs degradations appear to be very weak at the maximum TID of 6 MGy(SiO2), 600 Mrad. In the end, this study demonstrates the feasibility of a MGy rad-hard CMOS color digital camera-on-a-chip, illustrated by a color image captured after 6 MGy(SiO2) with no obvious degradation. An original dark current reduction mechanism in irradiated CMOS Image Sensors is also reported and discussed.

Pinned Photodiode CMOS Image Sensor TCAD Simulation: In-Depth Analysis of in-Pixel Pinning Voltage Measurement for a Diagnostic Tool

TCAD simulations are conducted on a pinned photodiode (PPD), with the aim to reproduce the pinning voltage measurement developed by Tan et al. A thermionic model is proposed and detailed in order to explain the exponential injection occurring at an injection voltage higher than the pinning voltage, and the correct method to extract the transfer gate inversion voltage is given. Then, various nonidealities are simulated, such as doping variations or doping layer shifts, the goal being to get a PPD diagnostic tool based on the pinning voltage measurement. Finally, the PPD is simulated in a real reading mode, and a charge partition mechanism is demonstrated in specific conditions.

Design Impact on Charge Transfer Inefficiency of Surface CCD on CMOS Devices: TCAD and Characterization Study

This paper presents a study of design optimization of charge-coupled device on CMOS devices, in order to minimize the charge transfer inefficiency (CTI). To achieve this goal, 3-D Technology Computer Aided Design (TCAD) simulations with a trap model at silicon-oxide interface were conducted, and measurements on two test chips manufactured on two different foundries were performed. TCAD simulations predict trends in agreement with measurements, but trap models at silicon trench isolation (STI) and gate oxides should be adapted accordingly to the technology used. Some design variations show results depending on the technology chosen, and the best CTI reduction is obtained with an increase of p-well inclusion over STI edges.

Dark Current Sharing and Cancellation Mechanisms in CMOS Image Sensors Analyzed by TCAD Simulations

Technology computer aided design (TCAD) simulations are conducted on a 4T PPD pixel, on a conventional gated photodiode (PD), and finally on a radiation hardened pixel. Simulations consist in demonstrating that it is possible to reduce the dark current due to interface states brought by the adjacent gate (AG), by means of a sharing mechanism between the PD and the drain. The sharing mechanism is activated and controlled by polarizing the AG at a positive OFF voltage, and consequently the dark current is reduced and not compensated. The drawback of the dark current reduction is a reduction of the full well capacity of the PD, which is not a problem when the pixel saturation is limited by the readout chain. Some measurements performed on pixel arrays confirm the TCAD results.