Omar Wing

Gate Matrix Layout

A graph-theoretic description of the problem of layout of CMOS circuits in the style of gate matrix in minimum area is presented. The problem is formulated as one of finding two assignment functions f and h such that the layout L(f, h) requires the minimum number of rows of the gate matrix. The function f maps the distinct gates of the transistors to the columns of the gate matrix and the function h maps the nets of the circuit to the rows such that all of the vertical diffusion runs which connect nets on different rows are realizable. A two-stage approach to the problem is described which first obtains a layout without regard to the vertical constraints and then rows are permuted to satisfy the constraints. Detailed algorithms and examples are given. The gate matrix layout of a 118-transistor circuit was obtained in 9 s on a mainframe computer.

SWITCAP: A switched-capacitor network analysis program part I: Basic features

The user aspects of a switched-capacitor network analysis program, SWITCAP, are discussed. The relation of the programs simulation facilities (such as frequency-domain analysis, time-domain analysis, and sampling functions) to actual laboratory measurement setups incorporating function generators, oscilloscopes, and spectrum analyzers is described in detail. Some examples illustrating the basic features of the program are also given.

Improved gate matrix layout

A two-stage approach to gate matrix layout is described. The approach consists of: the determination of an optimal gate sequence and an assignment of nets to rows such that the nets are realizable. The gate sequence algorithm is based on T. Asanos approximate search (1981). Modifications are made to it to take into account constraints of transistor sizing, serial subcircuit conflicts, input/output (I/O) gates, and I/O nets. The zone-net assignment algorithm assigns nets to a minimum number of rows determined by the gate sequence and provides a means to resolve vertical conflicts in the layout. Power connections are implemented using the power nets and possible added power rows. Results of examples show that the approach can achieve a considerable improvement compared to earlier algorithms, while satisfying additional constraints. >

Transient analysis of dispersive VLSI interconnects terminated in nonlinear loads

An algorithm for computing the transient response of a coupled, dispersive multiconductor system terminated in nonlinear loads is presented. The characterization of the multiconductor system is based on full-wave analysis using the spectral domain approach, rather than the usual TEM approximation. To compute the transient response of such a system, a bilevel waveform relaxation method is used. Waveform relaxation is applied to compute a time-domain solution at the input and output interfaces. The waveforms are then transformed into the frequency domain to compute the updates induced by the multiconductor system and are transformed back to the time domain for the next set of relaxation at the interfaces. Techniques for convergence are discussed. Examples of ECL, CMOS, and GaAs circuits connected by coupled lines are given for illustration. >

SWITCAP: A switched-capacitor network analysis program part II: Advanced applications

For pt.I see ibid., vol.5, no.3, p.4-10 (1983). The authors discuss the applications of a general switched-capacitor network (SCN) analysis program called SWITCAP for simulating SCNs containing continuous signal paths, clock feedthrough, resistors, finite-bandwidth amplifiers, and/or many phases.

Analysis of VLSI multiconductor systems by bi-level waveform relaxation

A novel algorithm to compute the transient response of a coupled, dispersive multiconductor system terminated in nonlinear loads such as transistors is developed. The characterization of the multiconductor system is obtained from a full-wave analysis based on the spectral domain approach, and it is suitable for circuit simulation. The transient response of such a system is computed by a bi-level waveform relaxation method. The solution process consists of two steps. One is to obtain a time domain solution at the input and output interfaces by local waveform relaxation, and the second is to transform the waveforms into the frequency domain and obtain the necessary updates for the next global relaxation step. The method allows the interconnects to be separated from the rest of the system so that both the nonlinear termination circuit and the multiconductor system can be analyzed in the most efficient way. The method has been applied to multiconductor systems terminated in MOS, ECL (emitter coupled logic), and GaAs transistors and it is shown that reflections and couplings can create logic errors in the system. The program that implements the algorithm is written in C.<<ETX>>

Circuit simulation by hierarchical waveform relaxation

A circuit analysis method, the hierarchical waveform relaxation technique, that uses multilevel decomposition and relaxation techniques is presented. Sufficient conditions for the convergence of the process are discussed, and a dynamic circuit restructuring technique that uses the concept of sensitivity based subcircuit merging and repartitioning within the hierarchical framework to improve the robustness of the simulation algorithm as well as the speed of convergence is presented. The algorithm is implemented in the circuit simulation program PYRAMID, and test results are compared with those obtained by other methods of analysis. The comparison indicates that this method produces better results than had previously been possible for a large range of circuits of practical interest, particularly strongly coupled digital bipolar and FET circuits containing bidirectionality and feedback, and it is demonstrated that the relative improvement of the method scales with the size of the circuit. >

A content-addressable systolic array for sparse matrix computation

Abstract A systolic array is proposed which is specifically designed to solve a system of sparse linear equations. The array consists of a number of processing elements connected in a ring. Each processing element has its own content-addressable memory where the nonzero elements of the sparse matrix are stored. Matrix elements to which elementary operations are applied are extracted from the memory by content addressing. The system of equations is solved in a systolic fashion and the solution is obtained in NZ + 5n − 2 steps, where NZ is the number of nonzero elements along and below the diagonal and n is the number of equations.

A C/sub infinity /-continuous depletion capacitance model

The p-n junction depletion capacitance models of the SPICE and ADVICE circuit simulators are regional models that have discontinuities in high-order derivatives. This limits the order of integration that can be used for transient analyses, and can limit both the size of time steps that can be used during transient analyses and the accuracy of distortion analyses. In addition, the SPICE and ADVICE depletion capacitance models unphysically predict that the depletion charge increases without bound as applied forward bias increases. An improved depletion capacitance model that overcomes these problems is presented. The model is charge-based, single-piece, and C/sub infinity /-continuous, and has a finite maximum junction depletion charge under forward bias. >

A circuit model of a system of VLSI interconnects for time response computation

A novel computational model based on the spectral-domain approach for the characterization of a dispersive multiconductor system is developed for time response computation. The model consists of two identical impedance networks and equivalent voltage-controlled voltage sources, and it is particularly suitable for timing analysis. Since the model is constructed based on full-wave analysis, the hybrid nature of the VLSI interconnects is taken care of, and thus the model is valid at high frequencies when the longitudinal field components are no longer negligible. Signal distortions due to the dispersive nature of a multiconductor system are demonstrated by an example. >