Omer H. Dokumaci

Silicon CMOS devices beyond scaling

To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.

Universal tunneling behavior in technologically relevant P/N junction diodes

Band-to-band tunneling was studied in ion-implanted P/N junction diodes with profiles representative of present and future silicon complementary metal–oxide–silicon (CMOS) field effect transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of capacitance versus voltage characteristics, and compared to secondary-ion mass spectroscopy analysis. When the tunneling current was plotted against the effective tunneling distance (tunneling distance corrected for band curvature) a quasi-universal exponential reduction of tunneling current versus, tunneling distance was found with an attenuation length of 0.38 nm, corresponding to a tunneling effective mass of 0.29 times the free electron mass (m0), and an extrapolated tunneling current at zero tunnel distance of 5.3×107 A/cm2 at 300 K. These results are directly applicable for predicting drain to substrate currents in CMOS transistors on bulk silicon, and body currents in CMOS transistors in silicon-on-insulator.

FinFET performance advantage at 22nm: An AC perspective

At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

Optimizing CMOS technology for maximum performance

Since power dissipation is becoming a dominant limitation on the continued improvement of CMOS technology, technologists must understand the best way to design transistors in the presence of power constraints. The primary objective is to obtain as much performance as possible for a fixed amount of power, and it is chip performance, not device performance, that matters. In order to investigate this regime, we have captured in simplified models the basic elements for determining chip performance, including intrinsic transistor characteristics, circuit delay, tolerance issues, basic microprocessor composition, and power dissipation and heat removal considerations. These models have been assembled in a processor-level technology-optimization program to study the characteristics of optimal technology across many generations of CMOS. The results that are presented elucidate the limits of future CMOS technology improvements, the optimal energy consumption conditions, and the relative benefits of various proposed technology enhancements, including high-k gate insulators, metal gates, high-mobility semiconductors, improved heat removal, and the use of multiple layers of circuitry.

Diffusion of implanted nitrogen in silicon

Growth of thinner gate oxides and their thickness control is one of many challenges in scaling technologies today. Nitrogen implantation can be used to control gate oxide thicknesses. This article reports a study on the fundamental behavior of nitrogen diffusion in silicon. Nitrogen was implanted as N2+ at a dose of 5×1013 ions/cm2 at 40 and 200 keV through a 50 A screen oxide into Czochralski silicon wafers. Furnace anneals at a range of temperatures from 650 to 1050 °C have revealed anomalous diffusion behavior. For the 40 keV implants, nitrogen diffuses very rapidly and segregates at the silicon/silicon-oxide interface. Qualitative modeling of this behavior is also discussed in terms of the time taken to create a mobile nitrogen interstitial through the kickout, Frenkel pair, and the dissociative mechanisms.

Experimental identification of nitrogen-vacancy complexes in nitrogen implanted silicon

Nitrogen implantation is commonly used in multigate oxide thickness processing for mixed signal complementary metal-oxide-semiconductor and System on a Chip technologies. Current experiments and diffusion models indicate that upon annealing, implanted nitrogen diffuses towards the surface. The mechanism proposed for nitrogen diffusion is the formation of nitrogen-vacancy complexes in silicon, as indicated by ab initio studies by J. S. Nelson, P. A. Schultz, and A. F. Wright [Appl. Phys. Lett. 73, 247 (1998)]. However, to date, there does not exist any experimental evidence of nitrogen-vacancy formation in silicon. This letter provides experimental evidence through positron annihilation spectroscopy that nitrogen-vacancy complexes indeed form in nitrogen implanted silicon, and compares the experimental results to the ab initio studies, providing qualitative support for the same.

Tunnel current measurements on P/N junction diodes and implications for future device design

Band-to-band tunneling was studied experimentally in ion-implanted PN junction diodes with profiles representative of present and future silicon CMOS transistors. Measurements were done over a wide range of temperatures and implant parameters. Profile parameters were derived from analysis of CV characteristics, and compared to SIMS analysis. When tunneling current was plotted against distance (tunneling distance, corrected for band curvature) a quasi-universal exponential reduction of tunneling current vs. tunneling distance was found with an attenuation length of 0.38 nm, and an extrapolated tunneling current at zero tunnel distance of 5.3/spl times/10/sup 7/ A/cm/sup 2/ at 300 K. These results were used to estimate drain-substrate currents in future scaled CMOS, and it was concluded that it will be challenging to make the ITRS 2002 roadmap projections on leakage current for the low operating power and low standby power options without more innovation and device design changes.

Physical integrated diffusion-oxidation model for implanted nitrogen in silicon

Scaling the gate oxide thickness is one of many process development challenges facing device engineers today. Nitrogen implantation has been used to control gate oxide thickness. By varying the dose of the nitrogen implant, process engineers can have multiple gate oxide thicknesses in the same process. Although it has been observed that nitrogen retards gate oxidation kinetics, the physics of how this occurs is not yet well understood. Since the retardation in oxide growth is due to the diffusion of nitrogen and its subsequent incorporation at the silicon/silicon oxide interface, the study of the diffusion behavior of nitrogen in silicon becomes important. Further, it is also necessary to study how this diffusion behavior impacts oxide growth. Models have been developed to explore these issues. The diffusion model is based on ab initio results and is compared to experimental results at two temperatures. The oxide reduction model is based on the diffusion of nitrogen to the surface. The surface nitrogen is...

Nitrogen-induced transient enhanced diffusion of dopants

Studies of both systematic experiments and detailed simulations for examining the effects of N2+ implant on channel dopants are described. Step-by-step monitor wafer experiments have clearly confirmed the nitrogen-induced transient enhanced diffusion (TED) of dopants. Process simulations within the “+1” N2+ profile approach have demonstrated the need to scale down the +1 model parameter for matching the measured depth profiles. The underlying mechanism for the reduced +1 model parameter is that nitrogen which diffuses toward the Si surface becomes a sink for the interstitials. These combined studies also show that nitrogen-induced TED of dopants increases with N2+ dose.

Comprehensive model for nitrogen diffusion in silicon

Nitrogen implantation allows the implementation of varying oxide thickness in the same process. At IEDM 2000, we have shown an integrated nitrogen diffusion-oxidation model to predict the gate oxide thickness. In this paper, we describe further experiments and modeling to explain the diffusion behavior of implanted nitrogen in silicon that lead to a substantial improvement in both the extent of data fit and understanding of the process physics. We show that the model is consistent with three new experimental studies. The improved model now predicts the formation of extended defects from nitrogen implants, correlates well with positron annihilation studies, and agrees with the diffusion results when the damage is changed by co-implants of silicon. The improved model is valid over a wider range of conditions.