Onat Menzilcioglu

The Warp Computer: Architecture, Implementation, and Performance

The Warp machine is a systolic array computer of linearly connected cells, each of which is a programmable processor capable of performing 10 million floating-point operations per second (10 MFLOPS). A typical Warp array includes ten cells, thus having a peak computation rate of 100 MFLOPS. The Warp array can be extended to include more cells to accommodate applications capable of using the increased computational bandwidth. Warp is integrated as an attached processor into a Unix host system. Programs for Warp are written in a high-level language supported by an optimizing compiler. The first ten-cell prototype was completed in February 1986; delivery of production machines started in April 1987. Extensive experimentation with both the prototype and production machines has demonstrated that the Warp architecture is effective in the application domain of robot navigation as well as in other fields such as signal processing, scientific computation, and computer vision research. For these applications, Warp is typically several hundred times faster than a VAX 11/780 class computer. This paper describes the architecture, implementation, and performance of the Warp machine. Each major architectural decision is discussed and evaluated with system, software, and application considerations. The programming model and tools developed for the machine are also described. The paper concludes with performance data for a large number of applications.

Warp architecture and implementation

This paper describes the scan line array processor (SLAP), a new architecture designed for high-performance yet low-cost image computation. A SLAP is a SIMD linear array of processors, and hence is easy to build and scales well with VLSI technology; yet appropriate special features and programming techniques make it efficient for a surprisingly wide variety of low and medium level computer vision tasks. We describe the basic SLAP concept and some of its variants, discuss a particular planned implementation, and indicate its performance on computer vision and other applications.

Host interface design for ATM LANs

ATM (asynchronous transfer mode) is an international telecommunications standard designed for broadband integrated services; it is also well-suited for use within local-area networks. ATM LANs can provide the networking support needed for multimedia communication at rates of 100 Mbits/sec and higher. The authors first analyze the protocol processing required to handle ATM communication. Based on this analysis, they then discuss the architectural issues in the design of host interfaces for ATM local-area networks. In particular, they conclude that a simple host interface, which leaves most of the ATM protocol processing to be done by the host computer, supports good performance for data communication (around 100 Mbits/sec). However, to support real-time video and audio communication, the ATM interface should include an embedded processor.<<ETX>>

Network-based multicomputers: an emerging parallel architecture

No abstract available

CARGuide: on-board computer for automobile route guidance

This paper describes the Computer for Automobile Route Guidance (CARGuide), a prototype system designed and built at Carnegie-Mellon University. CARGuide is a portable, microcomputer-based system to aid drivers in route finding and navigation in city streets. Given starting and destination intersections, CARGuide calculates an optimum route to the destination, displays portions of the street map containing the route, and highlights the streets on the route by flashing them on a display. It provides automatic or manual zooming into the map picture and speaks driving directions along the route. Both hardware and software design is explained in the paper. The hardware consists of a 68000 processor on a Multibus, bubble memories for secondary storage, a 128 x 128 dot matrix fluorescent display, a speech synthesizer, RAM, control and interface logic for the components, and a keyboard. A total of six circuit boards are used, four of them designed at CMU. A compact street map database is constructed from a regular street map and is stored in CARGuides half megabyte secondary storage. An efficient optimum route-finding scheme was implemented, which uses a divide and conquer method and precomputed routes to improve the performance of a shortest-path algorithm. For optimum route calculations, streets are given weights estimating the travel time, and penalties are introduced for turns and crossing intersections. CARGuide has been tested by implementing a portion of the Pittsburgh street map.

Warp architecture: From prototype to production

The Warp machine* is a high-performance systolic array computer with a linear array of 10 or more cells, each of which is a programmable processor capable of performing 10 million floating-point operations per second (10 MFLOPS). A 10-cell machine has a peak performance of 100 MFLOPS. Warp is integrated into a UNIXTM host system, and program development is supported by a compiler. Two copies of a 10-cell prototype of the Warp machine became operational in 1986 and are in use at Carnegie Mellon for a wide range of applications, including low-level vision processing for robot vehicle navigation and signal processing. The success of the prototypes led to the development of a production version of the Warp machine that is implemented with printed circuit boards. At least eight copies of this machine are being built by General Electric in 1987. The first copy was delivered to Carnegie Mellon in April 1987. This paper describes the architecture of the production Warp machine and explains the changes that turned the prototype system into a mature high-performance computing engine. * Warp is a service mark of Carnegie Mellon University.

Comprehensive evaluation of a two-dimensional configurable array

An evaluation is presented of a highly configurable architecture for two-dimensional arrays of powerful processors. The evaluation is based on an array of Warp cells and uses real application programs. The evaluation covers the areas of configurability, array survivability, and performance degradation. The software and algorithms developed for the evaluation are also discussed. The results based on simulations of small and medium size arrays (up to 16*16) show that a high degree of configurability and array survivability can be achieved with little impact on program performance.<<ETX>>

Warp: A Programmable Systolic Array Processor

CMU is currently building a programmable, 32-bit floating-point systolic array processor using only off-the-shelf components. The 10-cell processor, with one cell implemented on one board, can process 1024-point complex FFIs at a rate of one FFT every 600 μs. Under program control, the same processor can perform many other primitive computations in signal, image, and vision processing, including two-dimensional convolution, dynamic programming, and real or complex matrix multiplication, at a rate of 100 million floating-point operations per second. This particular systolic array processor is called the Warp, suggesting that it can perform a variety of transformations at a very high speed. For a mobile robot demonstration planned in 1985, the Warp is expected to speed up the navigation process by at least one order of magnitude. The Warp has a relatively simple architecture given its performance. The processor is a linear array of cells (or processing elements) that in general takes inputs from one end. and produces outputs at the other end. The processor can efficiently implement many systolic algorithms where communication between adjacent cells is intensive. The processor can also efficiently implement many non-systolic algorithms where each cell operates on its own data independently from the rest. This paper describes the structure of the Warp.

Using warp as a supercomputer in signal processing

Warp is a programmable systolic array machine designed by CMU and built together with its industrial partners-GE and Honeywell. The first large scale version of the machine with an array of 10 linearly connected cells will become operational in January 1986. Each cell in the array is capable of performing 10 million 32-bit floating-point operations per second (10 MFLOPS). The 10-cell array can achieve a performance of 50 to 100 MFLOPS for a large variety of signal processing operations such as digital filtering, image compression, and spectral decomposition. The machine, augmented by a Boundary Processor, is particularly effective for computationally expensive matrix algorithms such as solution of linear systems, QR-decomposition and singular value decomposition, that are crucial to many real-time signal processing tasks. This paper outlines the Warp implementation of the 2- dimensional Discrete Cosine Transform and singular value decomposition.

Nectar CAB: a high-speed network processor

Nectar is a high-speed fiber-optic network developed as a network backplane to support distributed and heterogeneous computing. A distinguishing component of the Nectar network is a highly programmable network processor called the communication accelerator board (CAB). The Nectar CAB has a flexible architecture, where almost all interactions between the network and the host are programmable. This structure allows arbitrary protocols to be implemented, evaluated, and utilized. A description is presented of the design, implementation, and usage of the Nectar CAB, and performance implications of its hardware features are discussed.<<ETX>>