Osamu Nomura

A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture

Hierarchical convolutional neural networks represent a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent vision systems, its VLSI implementation with high performance and low power consumption is required. This paper proposes a VLSI convolutional network architecture using a hybrid approach composed of pulse-width modulation (PWM) and digital circuits. We call this approach merged/mixed analog-digital architecture. The VLSI chip includes PWM neuron circuits, PWM/digital converters, digital adder-subtracters, and digital memory. We have designed and fabricated a VLSI chip by using a 0.35 μm CMOS process. The VLSI chip can perform 6-bit precision convolution calculations for an image of 100 × 100 pixels with a receptive field area of up to 20 × 20 pixels within 5 ms, which means a performance of 2 GOPS. Power consumption of PWM neuron circuits was measured to be 20 mW. We have verified successful operations using a fabricated VLSI chip.

An image filtering processor for face/object recognition using merged/mixed analog-digital architecture

This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and digital circuits. The LSI has been designed for implementing convolutional neural networks with a very large convolution-kernel size. The LSI designed using a 0.35 /spl mu/m CMOS performs 6-bit precision convolutions for an image of 80/spl times/80 pixels with a kernel size of up to 51/spl times/51 pixels within 8.2 ms. All operations for the fabricated LSI have been successfully verified. The power consumption estimated from SPICE simulation is 280 mW.

Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach

The hierarchical convolutional neural network models are considered promising for robust object detection/recognition. These models require huge computational power for performing a large number of multiply-and-accumulation (MAC) operations. In this paper, first we discuss efficient calculation schemes suitable for 2D MAC operations. Then we review the related algorithms and LSI architecture proposed in our previous work, in which we use a projection-field-type network architecture with sorting of neuron outputs by magnitude. For the LSI implementation, we adopt a merged/mixed analog-digital circuit approach using a large number of analog or pulse modulation circuits. We demonstrate the validity of our LSI architecture by testing proof-of-concept LSIs. It is essential to develop efficient and parallel A/D and D/A conversion circuits in order to connect a lot of on-chip analog circuits with the external digital system. In this paper, we also propose such an A/D conversion circuit scheme.

An image-filtering LSI processor architecture for face/object recognition using a sorted projection-field model based on a merged/mixed analog-digital architecture

Real-time object detection or recognition technology becomes more important for various intelligent vision systems. Processing models for object detection or recognition from natural images should tolerate pattern deformations and pattern position shifts. The hierarchical convolutional neural networks are considered as a promising model for robust object detection/recognition. This model requires huge computational power for a large number of multiply-and-accumulation operations. In order to apply this model to robot vision or various intelligent real-time vision systems, its LSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose an LSI architecture based on this algorithm. As a proof of concept for our LSI architecture, we have designed, fabricated and tested two test LSIs: a sorting LSI and an image-filtering LSI. The sorting LSI is designed based on the content addressable memory (CAM) circuit technology. The image-filtering LSI is designed for parallel processing by analog circuit array based on the merged/mixed analog-digital approach. We have verified the validity of our LSI architecture by measuring the LSIs.

A convolutional neural network VLSI architecture using sorting model for reducing multiply-and-accumulation operations

Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by sorting neuron outputs by magnitude. We also propose a VLSI architecture based on this algorithm. We have designed and fabricated a sorting LSI by using a 0.35 μm CMOS process. We have verified successful sorting operations at 100 MHz clock cycle by circuit simulation.

A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition

Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by thresholding in a projection field and by performing weight decomposition in a 2-D neuron array. We also propose a VLSI architecture based on the proposed algorithm, and estimate its operation performance.