Osamu Tamada

Analysis for collapse behavior of resist pattern in short develop time process using atomic force microscope

Adhesion property of resist is characterized with DPAT (direct peeling with atomic force microscope (AFM) tip) method using 193 nm resist patterns of 180 nm dot shape which were developed for various developing time between 12 and 120 seconds in order to analyze the phenomenon which the short develop time process had led to suppress the pattern collapse. Surface free energy and refractive index of resist film treated with the developing time were also investigated from a thermodynamic point of view. The balance model among surface energy was adopted for analyzing intrusion phenomenon of developer solution into the resist-substrate interface. It can be explained quantitatively that the intrusion energy of developer solution acts to weaken the adhesion strength of resist pattern to the substrate. Furthermore, the intrusion energy became larger with increasing developing time. Analysis with the DPAT method indicates that the pattern collapse occurs accompanied with interface and cohesion destruction. Interface-scientifically speaking, the short develop time process proved to be effective to suppress the pattern collapse because of higher adhesion energy of the resist pattern to the substrate in shorter developing time.

Immersion Lithography Bevel Solutions

The introduction of Immersion lithography, combined with the desire to maximize the number of potential yielding devices per wafer, has brought wafer edge engineering to the forefront for advanced semiconductor manufactures. Bevel cleanliness, the position accuracy of the lithography films, and quality of the EBR cut has become more critical. In this paper, the effectiveness of wafer track based solutions to enable state-of-art bevel schemes is explored. This includes an integrated bevel cleaner and new bevel rinse nozzles. The bevel rinse nozzles are used in the coating process to ensure a precise, clean film edge on or near the bevel. The bevel cleaner is used immediately before the wafer is loaded into the scanner after the coating process. The bevel cleaner shows promise in driving down defectivity levels, specifically printing particles, while not damaging films on the bevel.

Adhesion and removal of micro bubbles for immersion lithography

It is necessary to develop a nano-bubble detector similar as a conventional particle counter for reducing micro and nano defects caused by nano-bubble (NB) in immersion lithography. In this regard, we discuss adhesion and removal mechanisms of NB adhered on a resist surface for immersion lithography. The micro and nano bubbles are more likely to adhere to the micro defect on the resist surface and lens surface. Keeping cleanness of lens and resist surface is necessary in order to prevent the micro bubble adhesion. We employed the AFM (Atomic Force Microscope) for the observation of NBs on a Si substrate and a resist surface. The diameter and height of NBs observed are approximately 40~100nm and 3~8nm, respectively. By approaching the AFM tip onto the NBs, the repulsive force can be detected but the attractive force on the resist surface. The interaction analysis between the AFM tip and the ArF excimer resist surface is effective in order to identify the NBs and to distinguish from solid particles. These phenomena can be discussed on the basis of Lifshitz theory. The separation procedure of the NB is accomplished with the AFM tip. The applying load at which the NB can be separated into the minute one is approximately 5nN. In addition, by the thermodynamic analysis, it can be considered that the NB adhered on the resist surface tends to be a flat shape and spread on the resist surface. It is difficult to adhere the bubbles on the resist surface.

Investigation of coat-develop track system for EUV resist processing

EUV lithography (EUVL) is the leading candidate for the manufacture of devices with 1× nm node and beyond. However, many challenges remain for the industry to understand clearly and to overcome before EUVL will be ready for application in volume production. Efforts have been made to improve the various critical components of EUVL, such as light source, exposure tool, mask, resist material, and so on.[1,2] Among these, resist materials are considered as one of the most critical issues in realizing EUVL.[3,4] Coat-develop track system overcame several challenges for each traditional resist system (i.e. i-line, KrF ArF, and ArF immersion). EUV resist system requires ultra thin organic film coating.[5] The under-layer thickness is below 10nm and the resist thickness is about 40nm, however, in some cases film thickness is smaller than the diameter of particles on the substrate, even if the particle size is smaller than the detection limit of defect inspection tool. Also EUV resist patterning becomes extremely small pattern pitch. It leads the difficulty of CD control because the resist solubility in develop processing depends on resist type. Some resists were significantly swelled during develop process. Swelling depends on develop time and developer materials. That behavior on EUV resist system is becoming evident.[6] Furthermore, LWR improvement on track processing is required. During the conference, we will discuss how to coat the substrate with ultra thin film and how to control resist dissolution to improve CD uniformity and LWR. Additionally, we will show the latest lithographic results obtained with the novel application for EUV coat-develop track system.

Film stacking architecture for immersion lithography process

In immersion lithography process, film stacking architecture will be necessary due to film peeling. However, the architecture will restrict lithographic area within a wafer due to top side EBR accuracy In this paper, we report an effective film stacking architecture that also allows maximum lithographic area. This study used a new bevel rinse system on RF3 for all materials to make suitable film stacking on the top side bevel. This evaluation showed that the new bevel rinse system allows the maximum lithographic area and a clean wafer edge. Patterning defects were improved with suitable film stacking.

Analysis of the Effect of Mechanical Strength of the Resist Film on Pattern Collapse Behavior Using Atomic Force Microscope

Recently, pattern collapse is becoming one of the critical issues in semiconductor manufacturing and many works have been done to solve this issue1) 2). Since pattern collapse occurs when outer force onto the resist pattern such as surface tension, impact of rinse solution, etc. surpasses the resistance of the resist pattern such as mechanical strength, adhesion force between resist and substrate, it is considered effective for improvement of pattern collapse to control resist film properties by track process, i.e., optimization of the mechanical properties of the resist film and enhancement of the adhesion force between resist and substrate3) -5). In this study, we focused on the mechanical strength of the resist film and examined how post applied bake (PAB) condition affects the pattern collapse behavior. From ellipsometry measurement, it was found that increasing PAB time and temperature resulted in thickness reduction and refractive index increase, which suggested that the density of the resist film became high. Then we analyzed the mechanical strength of the resist film with the tip indentation method using atomic force microscope. It was found that the hardness of the resist film was affected by PAB conditions and regardless of PAB condition, hardened layer existed beneath the film surface. Finally, we carried out the measurements of loads to collapse 180nm resist dot patterns using the direct peeling with atomic force microscope tip (DPAT) method. Loads ranged from 600 to 2000nN overall and essentially increased as seen for indentation measurements when PAB temperature or time was increased, except some critical conditions. Through these evaluations using AFM, we succeeded in quantitatively evaluate the mechanical properties of the resist films processed with various PAB conditions. It was found that PAB condition obviously impacts on the hardness of the resist film and it is closely related to pattern collapse load.

Mechanical strength of resist film analyzed by tip indentation method

Mechanical strength of resist film processed by various post apply bake (PAB) conditions were measured utilizing the tip indentation method using atomic force microscope (AFM). With the tip indentation method, we could quantify mechanical strength of resist film in terms of “degree of softening.” It was found that PAB at our standard baking temperature tends to lead to softening of the resist film which is considered due to existence of softening point of the resist polymer. Also changing baking time at this temperature showed very complicated softness behavior. By control of baking temperature, we could obtain harder resist film as baking time becomes longer. Further analysis of these resist film properties by ellipsometry suggested that changes in mechanical strength occur by the evaporation of the resist solvent and/or structure changes inside the resist film, depending upon baking conditions.

Short develop time process with novel develop application system

A short develop time process was investigated and assessed in terms of various pattern features of a resist. Process latitude for a positive DUV resist was evaluated for various pitches of line-and-space patterns and contact hole patterns for different develop times. It was found that the process latitude, depth of focus (DOF) and exposure latitude (EL) were improved by shortening develop time for various pattern features. The characteristics of CD variation to develop time for each pattern feature agree with the suggestion in our previous paper that expanding resist process latitude was strongly correlated with the resist develop rate and that terminating the develop reaction while the resist develop rate remained large was the key to expanding the process latitude. The short develop time process contributed to the larger γ characteristics of the resist, a smaller thickness loss and also a lesser degree of surface roughness in the resist pattern, which led to an appropriate resist pattern for the semiconductor process. A novel develop application system was developed by considering the loci of movements of Dainippon Screen’s (DNS) slit-scan develop nozzle and a rinse nozzle on the wafer. It was found that the novel develop application system achieved highly accurate CD controllability while realizing the benefits of the short develop time process.

Improvement of resist process margin with short develop time process

Short develop time process was intensely investigated and characterized. Process margin for two different 193nm chemically amplified positive resists were analyzed for different develop times. It was found that the process margin, Exposure Latitude(EL) and Depth of Focus (DOF) for both resists is increased by shortened develop time. Resist develop rate and pattern wall angle characterization revealed that an improvement in process margin is strongly correlated to the resist develop rate and the key to obtain increased process margin is to terminate the develop reaction while the resist dissolution rate remains large. The “short develop time” benefits are suggested to result from the reduced dependence of the developed pattern on the latent image due to incomplete develop caused by the early termination of the develop reaction. Deeper investigation revealed the resist develop rate was affected by the develop application method as well as resist chemical differences. Dainippon Screen’s (DNS) slit-scan develop system is revealed to be very effective in controlling the resist develop rate because of its ability to apply the developer puddle very still and suitable for the short develop time process. It was also confirmed that the pattern collapse was reduced by shortening develop time. It is suggested this phenomenon is correlated to the penetration of developer into the resist-substrate interface as well as the change in pattern wall angle as a function of develop time. Post-develop defect levels have been confirmed for one 193nm resist over a range different develop times. This study revealed that develop time shortening resulted in fewer develop defects. In summary it is confirmed that short develop time process has the advantages of improved process margin for factors such as EL, DOF, pattern collapse, develop defects as well as throughput.

In-situ analysis of defect formation in coat develop track process

Typical defects to be resolved during coat-develop track processing have been confirmed during each resist generation; I-line, KrF, ArF, ArF immersion, and recently EUVV.[1-5] In this study, two types of defect formation were analyzed: organic film post coating non-uniformity spots and post develop water-marks. During substrate rotation,, a high-speed video camera is used to observe characteristic phenomena which lead to the generation of these rather typical defects. Post coating non-uniformity defects were linked to bubble formation, and post develop defects were associated with thee wafer drying conditions. By correlating high-speed camera images and defect inspection results from several different resists we can disclose the defect generation mechanism of multiple typical phenomena.