Oscar Almer

Scalable multi-core simulation using parallel dynamic binary translation

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core ×86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead.

A SPAD-Based Visible Light Communications Receiver Employing Higher Order Modulation

This paper studies complex modulation schemes, including orthogonal frequency-division multiplexing (OFDM), received by a single photon avalanche diode (SPAD) array integrated circuit (IC). A SPAD operates in the Geiger mode, and is able to detect single photons. This feature enables order of magnitude receiver sensitivity in intensity modulation (IM) / direct detection (DD) Visible Light Communication (VLC) systems. The tradeoff between received power and bit error ratio (BER) using both pulse-amplitude modulation (PAM) and OFDM is shown. A first order model of the noise in a digital SPAD receiver is derived. The noise in the experimental receiver chip approaches the predicted noise in our model, and we achieve receiver sensitivity of

4-PAM visible light communications with a XOR-tree digital silicon photomultiplier

-

60 Mb/s, 2 meters visible light communications in 1 klx ambient using an unlensed CMOS SPAD receiver

64 dBm with a 100 kbit/s signal at a BER of 10^-5. It is concluded that future improvements in SPAD VLC receiver architecture will allow sensitivity to approach the quantum limit.

Backside illuminated SPAD image sensor with 7.83μm pitch in 3D-stacked CMOS technology

We show reception of a higher order modulation scheme using a novel high-fill-factor XOR-tree based digital silicon photomultiplier array. We also demonstrate and model even-order XOR cancellation and nonlinear saturation resulting from this design.

A learning-based approach to the automated design of MPSoC networks

We demonstrate an optical link operating in indoor ambient lighting conditions using a CMOS single photon avalanche diode (SPAD) optical receiver and a RGB light emitting diode (LED). The high sensitivity of the SPAD receiver allows the link to operate at 2 m distance at a total 60 Mb/s and bit error rate (BER) of 1×10-3 without lensing. The transmitter implements color shift keying (CSK) using a custom 4-channel current mode CMOS digital to analog converter (DAC). The miniaturized, low cost components employed at transmitter and receiver are suited to integration in portable electronic devices or chip-in-a-bulb respectively.

Hypervelocity time-of-flight characterisation of a 14GS/s histogramming CMOS SPAD sensor

We present the first 3D-stacked backside illuminated (BSI) single photon avalanche diode (SPAD) image sensor capable of both single photon counting (SPC) intensity, and time resolved imaging. The 128×120 prototype has a pixel pitch of 7.83 μm making it the smallest pixel reported for SPAD image sensors. A low power, high density 40nm bottom tier hosts the quenching front end and processing electronics while an imaging specific 65nm top tier hosts the photo-detectors with a 1-to-1 hybrid bond connection [1]. The SPAD exhibits a median dark count rate (DCR) below 200cps at room temperature and 1V excess bias, and has a peak photon detection probability (PDP) of 27.5% at 640nm and 3 V excess bias.

A Parallel Dynamic Binary Translator for Efficient Multi-Core Simulation

Many embedded computing platforms are highly specialised towards a given task and, consequently, sacrifice generality for high performance and energy efficiency at low cost. It is commonly accepted that integrating multiple processor cores on the same chip is the most promising way of delivering a high level of processing power under tight energy and cost constraints. Whereas the customisation of individual processing elements to particular tasks such as DSP or multimedia functions is a well-studied problem, the specialisation of applicationspecific on-chip and off-chip interconnects between processing elements has been largely neglected. In this paper we explore the design space of a tree-based network on chip of a synthesisable application-specific MPSoC. We empirically deduce the optimal network configurations, in terms of runtime and energy consumption, for a range of benchmark workloads. We present a machine learning approach that is able to predict optimal, or near-optimal, network-on-chip configurations for a new and as-yet-unseen workload. This new approach to automated NoC design yields designs that are, on average, within 9% of optimal design for the given workload. Moreover, the model predicts network configurations based on sample data from a single profiling run of the new application on a reference platform, providing the answer up to 280 times faster than an exhaustive search

Selecting the optimal system: automated design of application-specific systems-on-chip

We present Time-of-Flight (TOF) distance, velocity and acceleration characterisation of a multi-event Time-to-Digital- Converter (TDC) optical sensor featuring a 32x32 Single Photon Avalanche Diode (SPAD) array, a 14 GS/s TDC and on-chip histogram generation. Events are continuously recorded on-chip in 264 70 ps-wide histogram bins. High TDC throughput enables the device to be operated in Doppler mode with pulse-trains moving at hypervelocity speeds relative to the operational sensor frequency. Electrical frequency-detuned signals of 50 kHz are resolved by the TDC module. Optical frequency-detuned signals of 1 kHz are resolved, corresponding to a TOF velocity resolution of 15.8 km/s. Linear, sine-wave, and chirp frequency modulation techniques are used to demonstrate these characteristics.

A CMOS SPAD Sensor With a Multi-Event Folded Flash Time-to-Digital Converter for Ultra-Fast Optical Transient Capture

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core x86 host machine for as many as 2,048 target processors whilst exhibiting minimal and near constant overhead, including memory considerations.