Otoniel López-Granado

GPU-based 3D lower tree wavelet video encoder

The 3D-DWT is a mathematical tool of increasing importance in those applications that require an efficient processing of huge amounts of volumetric info. Other applications like professional video editing, video surveillance applications, multi-spectral satellite imaging, HQ video delivery, etc, would rather use 3D-DWT encoders to reconstruct a frame as fast as possible. In this article, we introduce a fast GPU-based encoder which uses 3D-DWT transform and lower trees. Also, we present an exhaustive analysis of the use of GPU memory. Our proposal shows good trade off between R/D, coding delay (as fast as MPEG-2 for High definition) and memory requirements (up to 6 times less memory than x264).

Design and implementation of an efficient hardware integer motion estimator for an HEVC video encoder

High-Efficiency Video Coding (HEVC) was developed to improve its predecessor standard, H264/AVC, by doubling its compression efficiency. As in previous standards, Motion Estimation (ME) is one of the encoder critical blocks to achieve significant compression gains. However, it demands an overwhelming complexity cost to accurately remove video temporal redundancy, especially when encoding very high-resolution video sequences. To reduce the overall video encoding time, we propose the implementation of the HEVC ME block in hardware. The proposed architecture is based on (a) a new memory scan order, and (b) a new adder tree structure, which supports asymmetric partitioning modes in a fast and efficient way. The proposed system has been designed in VHDL (VHSIC Hardware Description Language), synthesized and implemented by means of the Xilinx FPGA, Virtex-7 XC7VX550T-3FFG1158. Our design achieves encoding frame rates up to 116 and 30 fps at 2 and 4K video formats, respectively.

Enhancing LTW image encoder with perceptual coding and GPU-optimized 2D-DWT transform

When optimizing a wavelet image coder, the two main targets are to (1) improve its rate-distortion (R/D) performance and (2) reduce the coding times. In general, the encoding engine is mainly responsible for achieving R/D performance. It is usually more complex than the decoding part. A large number of works about R/D or complexity optimizations can be found, but only a few tackle the problem of increasing R/D performance while reducing the computational cost at the same time, like Kakadu, an optimized version of JPEG2000. In this work we propose an optimization of the E_LTW encoder with the aim to increase its R/D performance through perceptual encoding techniques and reduce the encoding time by means of a graphics processing unit-optimized version of the two-dimensional discrete wavelet transform. The results show that in both performance dimensions, our enhanced encoder achieves good results compared with Kakadu and SPIHT encoders, achieving speedups of 6 times with respect to the original E_LTW encoder.

MPCM: a hardware coder for super slow motion video sequences

In the last decade, the improvements in VLSI levels and image sensor technologies have led to a frenetic rush to provide image sensors with higher resolutions and faster frame rates. As a result, video devices were designed to capture real-time video at high-resolution formats with frame rates reaching 1,000 fps and beyond. These ultrahigh-speed video cameras are widely used in scientific and industrial applications, such as car crash tests, combustion research, materials research and testing, fluid dynamics, and flow visualization that demand real-time video capturing at extremely high frame rates with high-definition formats. Therefore, data storage capability, communication bandwidth, processing time, and power consumption are critical parameters that should be carefully considered in their design. In this paper, we propose a fast FPGA implementation of a simple codec called modulo-pulse code modulation (MPCM) which is able to reduce the bandwidth requirements up to 1.7 times at the same image quality when compared with PCM coding. This allows current high-speed cameras to capture in a continuous manner through a 40-Gbit Ethernet point-to-point access.

Source Coding Options to Improve HEVC Video Streaming in Vehicular Networks

Video delivery in Vehicular Ad-hoc NETworks has a great number of applications. However, multimedia streaming over this kind of networks is a very challenging issue because (a) it is one of the most resource-demanding applications; (b) it requires high bandwidth communication channels; (c) it shows moderate to high node mobility patterns and (d) it is common to find high communication interference levels that derive in moderate to high loss rates. In this work, we present a simulation framework based on OMNeT++ network simulator, Veins framework, and the SUMO mobility traffic simulator that aims to study, evaluate, and also design new techniques to improve video delivery over Vehicular Ad-hoc NETworks. Using the proposed simulation framework we will study different coding options, available at the HEVC video encoder, that will help to improve the perceived video quality in this kind of networks. The experimental results show that packet losses significantly reduce video quality when low interference levels are found in an urban scenario. By using different INTRA refresh options combined with appropriate tile coding, we will improve the resilience of HEVC video delivery services in VANET urban scenarios.

Error Resilient Coding Techniques for Video Delivery over Vehicular Networks

Nowadays, more and more vehicles are equipped with communication capabilities, not only providing connectivity with onboard devices, but also with off-board communication infrastructures. From road safety (i.e., multimedia e-call) to infotainment (i.e., video on demand services), there are a lot of applications and services that may be deployed in vehicular networks, where video streaming is the key factor. As it is well known, these networks suffer from high interference levels and low available network resources, and it is a great challenge to deploy video delivery applications which provide good quality video services. We focus our work on supplying error resilience capabilities to video streams in order to fight against the high packet loss rates found in vehicular networks. So, we propose the combination of source coding and channel coding techniques. The former ones are applied in the video encoding process by means of intra-refresh coding modes and tile-based frame partitioning techniques. The latter one is based on the use of forward error correction mechanisms in order to recover as many lost packets as possible. We have carried out an extensive evaluation process to measure the error resilience capabilities of both approaches in both (a) a simple packet error probabilistic model, and (b) a realistic vehicular network simulation framework. Results show that forward error correction mechanisms are mandatory to guarantee video delivery with an acceptable quality level , and we highly recommend the use of the proposed mechanisms to increase even more the final video quality.

Influence of Dead Zone Quantization Parameters in the R/D Performance of Wavelet-Based Image Encoders

Uniform quantization schemas with dead zone are commonly used in image and video codecs. The design of these quantizers affects to the final R/D performance, being two of the quantizer parameters, the responsible for that variations: (a) the dead zone size and (b) the reconstruction point location inside each quantization step. We analyze how variations of these parameters, by means of a variable dead zone quantizer, affect to the R/D performance of wavelet-based image encoders, using three different quality metrics. We tune the quantizer for each image to obtain the optimum parameters that provide the best R/D behavior for each of the metrics for different rate ranges, without altering the rest of the encoder stages. We provide a general parameter set for each metric and rate range, to be used with other images to obtain important rate savings and better quality values for each metric.

Optimizing the image R/D coding performance by tuning quantization parameters.

Abstract Uniform quantization schemas with dead zone are widely used in image and video codecs. The design of these quantizers affects to the final R/D performance, being two of the quantizer parameters the responsible for that variations: the dead zone size and the reconstruction point location inside each quantization step. In this work we tune the quantizer to obtain the optimum quantization parameters that provide the best R/D behavior for different quality metrics and rate ranges. Based on a representative image set, we provide the quantization parameters to encode general imagery, with a R/D performance close to the optimum one. The same study was done including the Contrast Sensitivity Function in the quantization stage. After an exhaustive experimental test, the results show that the estimated quantization parameters are able to provide bit rate savings up to 11% at low and moderate bit rates without additional computational cost.

Shared Memory Tile-Based vs Hybrid Memory GOP-Based Parallel Algorithms for HEVC Encoder

After the emergence of the new High Efficiency Video Coding standard, several strategies have been followed in order to take advantage of the parallel features available in it. Many of the parallelization approaches in the literature have been performed in the decoder side, aiming at achieving real-time decoding. However, the most complex part of the HEVC codec is the encoding side. In this paper, we perform a comparative analysis of two parallelization proposals. One of them is based on tiles, employing shared memory architectures and the other one is based on Groups Of Pictures, employing distributed shared memory architectures. The results show that good speed-ups are obtained for the tile-based proposal, especially for high resolution video sequences, but the scalability decreases for low resolution video sequences. The GOP-based proposal outperforms the tile-based proposal when the number of processes increases. This benefit grows up when low resolution video sequences are compressed.

Evaluation of an HEVC hardware IME module using a SoC platform

In the HEVC standard, motion estimation is one of the most complex task of the video encoder, requiring a great percentage of the encoding time mainly due to (a) a large set of Coding Tree Unit partitioning modes, (b) the presence of multiple reference frames, and (c) the varying size of Coding Units in comparison with its predecessor H264/AVC. In addition, HEVC adopts Variable Block Size Motion Estimation to obtain advanced coding efficiency. In this work, we evaluate a hardware IME design when applied to an System-On-Chip platform. In this evaluation we will measure the impact on the Rate/Distortion performance when applying different CTU sizes and reference search areas. Furthermore, we will evaluate the effect of the DMA transfers required in the computational performance. This architecture has been synthesized and implemented on the Xilinx SoC, Zynq-7 Mini-ITX Motherboard XC7Z100 (xc7z100ffg900-2). We have evaluated our hardware IME design using different CTU size configurations, search area sizes and DMA burst sizes in order to determine the maximum speed gain respect to the HEVC reference software. Results show that (a) the overall encoding time could be reduced by 588 times, being the DMA transfer the bottleneck of our design; (b) Rate/Distortion performance has no significant variations when using different CTU and search area configurations; (c) the encoding delay will strongly depend on the size of both CTU and search area sizes.