Ozgur Sinanoglu

Peak Power Reduction Through Dynamic Partitioning of Scan Chains

Serial shift operations in scan-based testing impose elevated levels of power dissipation, endangering the reliability of the chip being tested. Scan chain partitioning techniques are quite effective in reducing test power, as the rippling in the clock network, in the scan chains, and in the combination logic is reduced altogether. Partitioning approaches implemented in a static manner may fail to reduce peak power down to the desired level, however, depending on the transition distribution of the problematic pattern in the statically constructed scan chain partitions. In this paper, we propose a dynamic partitioning approach capable of adapting to the transition distribution of any test pattern, and thus of delivering near-perfect peak power reductions. We formulate the scan chain partitioning problem via integer linear programming (ILP) and also propose an efficient greedy heuristic. The proposed partitioning hardware allows for the partitioning reconfiguration on a per test pattern basis, enabling the dynamic partitioning. Significant peak power reductions are thus attained cost-effectively.

Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test

Scan chain partitioning techniques are quite effective in reducing test power, as the rippling in the clock network, scan chains, and logic is reduced altogether. Partitioning approaches implemented in a static manner may fail to reduce peak power down to the desired level, however, depending on the transition distribution of the problematic pattern in the statically constructed scan chain partitions. In this paper, we propose a dynamic partitioning approach capable of adapting to the transition distribution of any test pattern and, thus, of delivering near-perfect peak power reductions. The proposed dynamic partitioning hardware allows for the partitioning reconfiguration on a per test pattern basis, hence delivering a solution that is test set independent, yet its quality is superior to that of any test set dependent solution.

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing

Containing production cost is a major concern for todays complex SoCs. One of the key contributors to production cost is test time and test data volume, for which numerous compression techniques were proposed. This article introduces a different approach to test data volume reduction, namely the use of modular test based on IEEE Std 1500 architecture, and it provides modeling, analysis, and quantification to support the proposed approach.

An Inherently Stabilizing Algorithm for Node-To-Node Routing over All Shortest Node-Disjoint Paths in Hypercube Networks

The node-disjoint paths problem deals with finding node-disjoint paths from a source node s to target node t, where t ¿ s. Two paths from s to t are said to be node-disjoint iff they do not have any common vertices except for their endpoints. Distributed solutions to the node-disjoint paths problem have numerous applications such as secure message transmission, reliable routing, and network survivability. In this paper, we present a simple distributed algorithm that is both stabilizing and inherently stabilizing under a realistic model that describes system interfaces and implementation issues in detail to route messages over all shortest node-disjoint paths from one process to another in an n-dimensional hypercube network.

Scan Architecture With Align-Encode

Scan architectures that provide compression capabilities have become mandatory due to the unbearable test costs imposed by high test data volume and prolonged test application. To alleviate these test costs, a stimulus decompressor and a response compactor block are inserted between the tester channels and the scan chains. As a result, a few tester channels drive a larger number of scan chains. In such an architecture, whether a particular test pattern can be delivered depends on the care bit distribution of that pattern. In this paper, we introduce a hardware block to be utilized in conjunction with a combinational stimulus decompressor block. This block, namely, Align-Encode, provides a deterministic per pattern control over care bit distribution of test vectors, improving pattern deliverability, and thus, the effectiveness of the particular stimulus decompressor. Align-Encode is reconfigured on a per pattern basis to delay the shift-in operations in selected scan chains. The number of cycles that a chain may be delayed can be between zero and the maximum allowable value, in order to align the scan slices in such a way that originally undeliverable test vectors become encodable. The reconfigurability of Align-Encode provides a test pattern independent solution, wherein any given set of test vectors can be analyzed to compute the proper delay information. We present efficient techniques for computing the scan chain delay values that lead to pattern encodability. Experimental results also justify the test pattern encodability enhancements that Align-Encode delivers, enabling significant test quality improvements and/or test cost reductions.

Diagnosis, modeling and tolerance of scan chain hold-time violations

Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of manufactured chips. In this paper, we propose a set of techniques that enable the accurate pinpointing of hold time violating scan cells, their modeling and tolerance, paving the way for the generation of valid test data that can be used to test chips with such systematic failures. The process yield is thus restored, as chips that are functional in mission mode can still be identified and shipped out, despite the existence of scan chain hold time failures. The techniques that we propose are non-intrusive, as they utilize only basic scan capabilities, and thus impose no design changes. Scan cells with hold time violations can be identified with maximal possible resolution, enabling the incorporation of the associated impact during the ATPG process and thus the generation of valid test data for the chips with such systematic failures

X-Align: Improving the Scan Cell Observability of Response Compactors

While response compaction reduces the size of expected vectors that need to be stored on tester memory, the consequent information loss inevitably reflects into loss in test quality. Unknown xs further exacerbate the quality loss problem, as they mask out errors captured in other scan cells in the presence of response compactors. In this paper, we propose a technique that manipulates the x distribution in scan responses prior to their propagation into the response compactor. A block, which we refer to as x-align, inserted between the scan chains and the response compactor aligns response xs within the same slices as much as possible in order to increase the number of scan cells that can be observed through the compactor. The alignment of xs is achieved by delaying the scan-out operations in the scan chains, wherein the proper delay values are computed judiciously. We present an Integer Linear Programming (ILP) formulation and a computationally efficient greedy heuristic for the computation of the delay values for scan chains. The x-align hardware is generic yet reconfigurable. An analysis of x distribution in a captured response helps compute the proper delay values, with which x-align is reconfigured to maximize the alignment of xs. The scan cell observability enhancement delivered by x-align paves the way for the utilization of simple response compactors, such as parity trees, yet providing high levels of test quality even in the presence of a large density of response xs. X-align can also be utilized with any response compactor to manipulate the x distribution in favor of the compactor, thus improving the test quality attained.

A non-intrusive isolation approach for soft cores

Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mechanism can provide controllability and observability at the core I/O interface, its implementation may have various implications on area, functional timing, test time and data volume, and at-speed coverage on the core interface. This paper proposed a non-intrusive core isolation technique that is based on the utilization of existing core registers for isolating the core. The authors provide a core register partitioning algorithm that is capable of identifying the core interface registers, and of robustly isolating a core, resulting in a computationally efficient core isolation implementation that is area and performance efficient at the same time. The proposed isolation technique also ensures minimal test time increase and no at-speed coverage loss on the core interface, offering an elegant solution for soft cores, and thus enabling significant SOC test cost reductions

Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors

While test stimulus compression helps reduce test time and data volume, and thus alleviates test costs, the delivery of certain test vectors may not be possible, leading to test quality degradation. Whether a test vector is encodable in the presence of a decompressor strongly hinges on the distribution of its care bits. In this paper, we present a technique that provides an on-chip capability to judiciously manipulate care bit distribution of a test vector. We thus propose a hardware block, namely, Align-Encode, to be utilized along with any decompressor to boost the effectiveness of the decompressor. Align-Encode is reconfigured on a per pattern basis to delay the shift-in operations in selected scan chains, in order to align the scan slices in such a way that more test vectors become encodable. The reconfigurability of Align-Encode provides a test pattern independent solution, wherein any given set of test vectors can be analyzed to compute the proper delay information. We map the delay computation problem to the maximal clique problem, and utilize an efficient heuristic to provide a near-optimal solution. Experimental results also justify the test pattern encodability enhancements that Align-Encode delivers, enabling significant test quality improvements and/or test cost reductions even when used with simple decompressors.

Analysis of the test data volume reduction benefit of modular SOC testing

Modular SOC testing offers numerous benefits that include test power reduction, ease of timing closure, and test re-use among many others. While all these benefits have been emphasized by researchers, the test time and data volume comparisons has been mostly constrained within the context of modular SOC testing only, by comparing the impact of various different modular SOC testing techniques to each other. In this paper, we provide a theoretical test data volume analysis that compares the monolithic test of a flattened design with the same design tested in a modular manner; we present numerous experiments that gauge the magnitude of this benefit. We show that the test data volume reduction delivered by modular SOC testing directly hinges on the test pattern count variation across different modules, and that this reduction can exceed 99% in the SOC benchmarks that we have experimented with.