P. Dimitrakis

Manipulation of two-dimensional arrays of Si nanocrystals embedded in thin SiO2 layers by low energy ion implantation

In silicon nanocrystal based metal–oxide–semiconductor memory structures, tuning of the electron tunneling distance between the Si substrate and Si nanocrystals located in the gate oxide is a crucial requirement for the pinpointing of optimal device architectures. In this work it is demonstrated that this tuning of the “injection distance” can be achieved by varying the Si+ ion energy or the oxide thickness during the fabrication of Si nanocrystals by ultralow-energy silicon implantation. Using an accurate cross-section transmission electron microscopy (XTEM) method, it is demonstrated that two-dimensional arrays of Si nanocrystals cannot be positioned closer than 5 nm to the channel by increasing the implantation energy. It is shown that injection distances down to much smaller values (2 nm) can be achieved only by decreasing the nominal thickness of the gate oxide. Depth profiles of excess silicon measured by time-of-flight secondary ion mass spectroscopy and Si nanocrystal locations determined by XTEM ...

Hybrid silicon-organic nanoparticle memory device

We demonstrate a nonvolatile electrically erasable programmable read-only memory device using gold nanoparticles as charge storage elements deposited at room temperature by chemical processing. The nanoparticles are deposited over a thermal silicon dioxide layer that insulates them from the device silicon channel. An organic insulator deposited by the Langmuir–Blodget technique at room temperature separates the aluminum gate electrode from the nanoparticles. The device exhibits significant threshold voltage shifts after application of low-voltage pulses (⩽±6 V) to the gate and has nonvolatile retention time characteristics.

Effect of annealing environment on the memory properties of thin oxides with embedded Si nanocrystals obtained by low-energy ion-beam synthesis

The effect of annealing in diluted oxygen versus inert environment on the structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals fabricated by very low-energy silicon implantation (1 keV) is reported. Annealing in diluted oxygen increases the thickness of the control oxide, improves the integrity of the oxide and narrows the size distribution of the nanocrystals without affecting significantly their mean size (∼2 nm). Strong charge storage effects at low gate voltages and enhanced charge retention times are observed through electrical measurements of metal-oxide-semiconductor capacitors. These results indicate that a combination of low-energy silicon implants and annealing in diluted oxygen allows for the fabrication of improved low-voltage nonvolatile memory devices.

Graphene‐Modified Interface Controls Transition from VCM to ECM Switching Modes in Ta/TaOx Based Memristive Devices

By modification of the electrode-solid-electrolyte interface with graphene, transit from valence change memories (VCM) to electrochemical metallization memories (ECM) in the cell Ta(C)/Ta2 O5 /Pt is demonstrated, thus, bridging both mechanisms. The ECM operation is discussed in the light of Ta-cation mobility in TaOx . The crucial role of electrochemical processes and moisture in the resistive switching process is also highlighted.

Oxidation of Si nanocrystals fabricated by ultralow-energy ion implantation in thin SiO2 layers

The effect of thermal treatments in nitrogen-diluted oxygen on the structural characteristics of two-dimensional arrays of Si nanocrystals (NCs) fabricated by ultralow-energy ion implantation (1 keV) in thin silicon dioxide layers is reported. The NC characteristics (size, density, and coverage) have been measured by spatially resolved electron-energy-loss spectroscopy by using the spectrum-imaging mode of a scanning transmission electron microscope. Their evolution has been studied as a function of thermal treatment duration at a temperature (900 °C) below the SiO2 viscoelastic point. An extended spherical Deal-Grove [J. Appl. Phys. 36, 3770 (1965)] model for self-limiting oxidation of embedded silicon NCs has been carried out. It proposes that the stress effects, due to oxide deformation, slow down the NC oxidation rate and lead to a self-limiting oxide growth. The model predictions show a good agreement with the experimental results. Soft oxidation appears to be a powerful way for manipulating the NC s...

Electrical behavior of memory devices based on fluorene-containing organic thin films

We report on switching and negative differential resistance (NDR) behaviors of crossed bar electrode structures based on Al/organic layer/Al devices in which the organic layer was a spin-coated layer of 7-{4-[5-(4-tert-butylphenyl)-1,3,4-oxadiazol-2-yl]phenyl}-9,9-dihexyl-N,N-diphenyl-fluoren-2-amine. The addition of gold nanoparticles (0.5wt%) did not change the switching behavior of thicker film structures; however, devices incorporating the nanoparticles showed more reproducible characteristics. In most cases, a “forming” process, in which a large positive voltage was applied to the top Al electrode, was required before the NDR and conductivity switching were observed. Three different electrical conductivity mechanisms have been identified: Poole–Frenkel conductivity in unformed structures, linear current versus voltage characteristics for the ON state in formed devices, and superlinear current versus voltage behavior for the OFF state in formed devices. Models based on metallic filaments or on the inj...

Oxide–nitride–oxide dielectric stacks with Si nanoparticles obtained by low-energy ion beam synthesis

Formation of a thin band of silicon nanoparticles within silicon nitride films by low-energy (1 keV) silicon ion implantation and subsequent thermal annealing is demonstrated. Electrical characterization of metal–insulator–semiconductor capacitors reveals that oxide/Si-nanoparticles-nitride/oxide dielectric stacks exhibit enhanced charge transfer characteristics between the substrate and the silicon nitride layer compared to dielectric stacks using unimplanted silicon nitride. Attractive results are obtained in terms of write/erase memory characteristics and data retention, indicating the large potential of the low-energy ion-beam-synthesis technique in SONOS memory technology.

Effects of annealing conditions on charge storage of Si nanocrystal memory devices obtained by low-energy ion beam synthesis

The structural and electrical characteristics of thin silicon dioxide layers with embedded Si nanocrystals are reported fabricated by low-energy silicon implantation and with subsequent annealing in inert and diluted oxygen. Thermal treatment in diluted oxygen increases the thickness of the control oxide, does not affect significantly the size of the nanocrystals, and improves the integrity of the oxide. As a result, strong charge storage effects at low gate voltages and enhanced charge retention times are observed through electrical measurements of MOS capacitors. These results indicate that a combination of low-energy silicon implants and annealing in diluted oxygen permits the fabrication of low-voltage nonvolatile memory devices.

GaN quantum-dots integrated in the gate dielectric of metal-oxide-semiconductor structures for charge-storage applications

Gallium nitride quantum dots (QDs) were investigated as discrete charge storage nodes embedded in the gate dielectric of metal-oxide-semiconductor (MOS) capacitors. The GaN QDs were formed on top of 3.5 nm-thick SiO2/n-Si(001) substrates by radiofrequency plasma-assisted molecular beam deposition. The MOS structures were studied by transmission electron microscopy. Deposition dose was determined as a critical process parameter to obtain two dimensional arrays of discrete QDs. The memory window width, programming speed, and charge retention time were evaluated for GaN QD devices with different deposition doses. All devices showed enhanced electron trapping leading to significant memory windows. Charge retention measurements, at room temperature, revealed that the sample with the lowest concentration of QDs exhibits a low charge loss with a significant extrapolated programming window after 10 yrs. The present study not only demonstrates GaN QD embedded SiO2 structures fabricated by a fully complementary met...

Controlled fabrication of Si nanocrystal delta-layers in thin SiO2 layers by plasma immersion ion implantation for nonvolatile memories

Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO2 films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories.