P.H. Woerlee

RF-CMOS performance trends

The impact of scaling on the analog performance of MOS devices at RF frequencies was studied. Trends in the RF performance of nominal gate length NMOS devices from 350-nm to 50-nm CMOS technologies are presented. Both experimental data and circuit simulations with an advanced validated compact model (MOS Model 11) have been used to evaluate the RF performance. RF performance metrics such as the cutoff frequency, maximum oscillation frequency, power gain, noise figure, linearity, and 1/f noise were included in the analysis. The focus of the study was on gate and drain bias conditions relevant for RF circuit design. A scaling methodology for RF-CMOS based on limited linearity degradation is proposed.

A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions

Abstract The transistor parameters of state-of-the-art MOSFETs are affected by quantisation effects of the carrier motion in the inversion channel. To account for these effects in classical device stimulators, we show that a better modeling of the silicon bandgap at inversion conditions is ifE g QM = E g CONV + 13 9 Δϵ in which Δϵ is the position of the first energy level with respect to the bottom of the conduction band. The improved modeling of the bandgap leads to a new model for the intrinsic carrier concentration ni. The model for ni has been tested against measurements and against self-consistent QM calculations. Excellent agreement is obtained.

Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs

The high levels of substrate doping needed in deep-submicrometer MOS devices affect device properties strongly. The authors present a detailed experimental study of high-doping effects on the threshold voltage, which is shown to be affected by the quantum-mechanical splitting of the energy levels in the conduction band. A simple expression to account for these effects is proposed and the consequences for device scaling and design are discussed. Furthermore, the increasing levels of substrate doping and high normal electric fields affect the channel mobility through Coulomb and surface-roughness scattering. Several empirical models for the surface mobility are compared with the characteristics of experimental devices. >

Non-local impact ionization in silicon devices

In small bipolar and MOS transistors, the electrons gain much less energy than according to the maximum electric field. This is due to nonlocal electron heating and the small width of the E-field peak. The simplified energy balance equation with the energy relaxation length lambda /sub e/ as parameter gives the electron temperature for a given electric field distribution. From a series of MBE (molecular beam epitaxy)-grown bipolar transistors and scaled submicron MOS transistors, lambda /sub e/=650 AA was found. With the calculated temperature distribution and known empirical models for the impact ionization, avalanche (substrate) currents are accurately predicted. This procedure can easily be implemented, as postprocessing, in existing device simulators with hardly any extra computation time. It extends in a consistent way the validity range of these simulators to future device generations.<<ETX>>

Accurate thermal noise model for deep-submicron CMOS

Extensive measurements of drain current thermal noise are presented for 3 different CMOS technologies and for gate lengths ranging from 2 /spl mu/m down to 0.17 /spl mu/m. Using a surface-potential-based compact MOS model with improved descriptions of carrier mobility and velocity saturation, all the experimental results can be described accurately without invoking carrier heating effects or introducing additional parameters.

A novel high-density low-cost diode programmable read only memory

A new stand-alone diode programmable read only memory (DPROM) technology for one-time-programmable memories is presented. The technology features small cell size and low mask count. The memory function is based on the formation of a diode-antifuse by gate oxide breakdown. The functionality of DPROM circuits is demonstrated and the program, read and reliability characteristics are discussed.

Three hot-carrier degradation mechanisms in deep-submicron PMOSFET's

Hot-carrier degradation is mainly caused by negative oxide-charge generation in the present-day PMOSFETs. We present experimental evidence showing that two more degradation mechanisms are important in the case of deep-submicron PMOSFETs. Firstly, the generation of interface states is significant in the case of sub-half-micron PMOSFETs. It even limits the lifetime of surface-channel transistors. Secondly, the generation of positive oxide charge by holes influences the characteristics. The latter process has been established unambiguously for the first time in PMOSFETs. We measured the bias dependence, the length dependence, and the time dependence separately for all three microscopic degradation mechanisms. We calculated the influence of these three mechanisms on the transconductance degradation. Summation of the three effects yields an excellent description of the experimentally determined time dependence of PMOSFET degradation for many bias conditions and various transistor geometries with either nitrided or conventional gate oxide. >

Dependency of dishing on polish time and slurry chemistry in Cu CMP

In this paper the influences of slurry chemistry and thickness of the copper layer on dishing will be discussed. The dishing is studied for different patterns and variable polishing times. We found that the concentration of the oxidiser and the thickness of copper layer have a strong impact on dishing. The larger Cu features develop dishing at a higher rate than smaller structures during overpolishing. The experimental results lead to the following hypothesis for the Cu removal and surface passivation. The oxidizer (H2O2) reacts with Cu in an acidic slurry (pH 4) and Cu2+ ions are formed. The anions of the carboxylic acid react with Cu2+ ions and form an insoluble salt (R(COO)2Cu) which passivates the surface. This passivation layer is removed in protruding areas by mechanical abrasion. Once removed from the surface, the ‘metallic soap’ particles are swept away by the turbulent motion in the slurry.

Diffusion and electrical properties of Boron and Arsenic doped poly-Si and poly-

In this paper the texture, morphology, diffusion and electrical (de‐) activation of dopants in polycrystalline GexSi1-x and Si have been studied in detail. For gate doping B+,BF2+ and As+ were used and thermal budgets were chosen to be compatible with deep submicron CMOS processes. Diffusion of dopants is different for GeSi alloys, B diffuses significantly more slowly and As has a much faster diffusion in GeSi. For B doped samples both electrical activation and mobility are higher compared to poly‐Si. Also for the first time, BF2+ data of doped layers are presented, these show the same trend as the B doped samples but with an overall higher sheet resistance. For arsenic doping, activation and mobility are lower compared to poly‐Si, resulting in a higher sheet resistance. The dopant deactivation due to long low temperature steps after the final activation anneal is also found to be quite different. Boron‐doped GeSi samples show considerable reduced deactivation whereas arsenic shows a higher deactivation rate. The electrical properties are interpreted in terms of different grain size, quality and properties of the grain boundaries, defects, dopant clustering, and segregation, and the solid solubility of the dopants.

Ge_xSi_1-x(x~0.3)

The distortion behaviour of MOSFETs is important for RF-applications. In this paper the influence of technology variations (oxide thickness, substrate doping,...) on distortion is investigated using measurements and a recently developed compact MOSFET model. The influence on distortion of technology scaling down to 0.18 /spl mu/m is verified and further scaling according to the ITRS-roadmap is predicted.