P. Jamison

Ultrathin high-K gate stacks for advanced CMOS devices

Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at Ioff = 300 pA/µm, VDD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

Band-Edge High-Performance High-k/Metal Gate n-MOSFETs Using Cap Layers Containing Group IIA and IIIB Elements with Gate-First Processing for 45 nm and Beyond

We have fabricated electrically reliable band-edge (BE) high-k/metal nMOSFETs stable to 1000degC, that exhibit the highest mobility (203 cm2/Vs @ 1MV/cm) at the thinnest Tinv (1.4 nm) reported to date. These stacks are formed by capping HfO2 with ultra-thin layers containing strongly electropositive gp. IIA and IIIB elements (e.g. Mg and La), prior to deposition of the TiN/Poly-Si electrode stack, in a conventional gate-first flow. Increasing the cap thickness tunes the Vt/V fb from a midgap position to BE while maintaining high mobility and good PBTI. The addition of La can enhance the effective k value of the dielectric stack, resulting in EOTs < 1nm. Short channel devices with band edge characteristics are demonstrated down to 60 nm. Finally, possible mechanisms to explain the nFET Vt shift are discussed

Role of oxygen vacancies in V FB /V t stability of pFET metals on HfO 2

We demonstrate experimentally that the flatband/threshold voltages (V/sub FB//V/sub t/) of pFET metal gates are strongly dependent on the post-deposition annealing conditions of the gate stacks. By varying the temperature and the O/sub 2/ partial pressure during post-deposition N/sub 2//O/sub 2/ and/or forming gas annealing (FGA) with Re, Ru and Pt, the gate stack V/sub FB/ can change by as much as 750 mV. However, using Re as an example, it is shown that conditions can be optimized and V/sub FB//V/sub t/-tuning for pFETs can be achieved for aggressively scaled stacks. It is proposed that charge transfer from oxygen vacancies to the gate electrode, possible only for high workfunction metal gates, leads to the formation of a dipole layer near the gate which can shift V/sub FB//V/sub t/. The results indicate that V/sub FB//V/sub t/ control remains a formidable processing challenge with high workfunction metals on HfO/sub 2/.

Thermally robust dual-work function ALD-MN/sub x/ MOSFETs using conventional CMOS process flow

Thermally stable dual work function metal gates are demonstrated using a conventional CMOS process flow. The gate structure consists of poly-Si/metal nitrides (MN/sub x/) SiON (or high-k)/Si stack with atomic layer deposition (ALD)-TaN/sub x/ for the NFET and ALD-WN/sub x/ for the PFET. Much enhanced drive current (I/sub d/) and transconductance (G/sub m/) values, and reduced off current (I/sub off/) characteristics were attained with ALD-MN/sub x/ gated devices over control poly-Si and PVD-MN/sub x/ devices within controllable V/sub t/ shifts. Excellent scalability of dual work function MN/sub x//high-k gate stack was demonstrated: the EOT was down to 6.6/spl Aring/ with low leakage in a low thermal budget device scheme.

Systematic study of pFET V/sub t/ with Hf-based gate stacks with poly-Si and FUSI gates

The flatband/threshold voltages (V/sub fb//V/sub t/) in poly-Si gated pFETs with Hf-based gate dielectrics are shown to be set during poly-Si deposition and are found to remain virtually unchanged during gate implantation and activation, independent of the p-type dopant. The reaction of Si with HfO/sub 2/ at poly-Si deposition temperatures is identified as the root cause for the poor V/sub fb//V/sub t/ control. No improvement in V/sub t/ control is obtained by engineering physically closed Si/sub 3/N/sub 4/ barrier layers on HfO/sub 2/. It is furthermore shown for the first time that even when the gate is fully silicided (FUSI) large V/sub fb//V/sub t/ shifts are observed with HfO/sub 2/. Reduced pFET shifts are observed when Hf-silicates with low Hf content are used and further improvements are observed by using Al/sub 2/O/sub 3/ cap layers on silicates.

Extremely thin SOI (ETSOI) technology: Past, present, and future

As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high-/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm (due to: (i) elimination of poly depletion effect, /spl sim/ 0.5 nm, and (ii) the high mobility of HfSi/sub x/O/sub y/). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)/spl sim/ -0.4 V and Vt(NFET) /spl sim/ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V/sub t/ stability) was found in the case of NiSi/ HfSi/sub x/O/sub y/ compared to the same gate electrode with HfO/sub 2/ dielectric.

80 nm polysilicon gated n-FETs with ultra-thin Al/sub 2/O/sub 3/ gate dielectric for ULSI applications

This work demonstrates the integration of Al/sub 2/O/sub 3/ gate-dielectrics into a sub 0.1 /spl mu/m n-MOS process using polycrystalline silicon gates, Devices incorporating Al/sub 2/O/sub 3/ films with a dielectric constant /spl epsi/-11 and electrical thickness t/sub qm/<1.5 nm have been fabricated. Gate leakage currents are /spl sim/100 times lower than those found in SiO/sub 2/ films of equivalent thickness. Encouraging device characteristics are shown. Charging due to slow states and/or fixed charge have been shown to be in the 100 mV range which may be related to the somewhat reduced mobility. The room temperature reliability of these devices based upon the values of /spl beta/ (Weibull slope) and /spl gamma/ (voltage acceleration) suggest that the Al/sub 2/O/sub 3/ lifetime may exceed that of SiO/sub 2/ films.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity to random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption for mainstream CMOS. This is especially true for low-power applications, where SOI wafer cost is deemed to significantly add to the total cost. We have recently reported a novel integration scheme to overcome some of the major ETSOI manufacturing issues such as difficulty in doping thin silicon layer, process induced silicon loss, and the dilemma of reduction of external resistance and the increase of parasitic capacitance [1, 2]. The proposed integration flow significantly simplifies device processing and leads to considerable reduction in the number of critical masks [2].