P. Moens

Hot-carrier degradation phenomena in lateral and vertical DMOS transistors

The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS.

Characterization of Total Safe Operating Area of Lateral DMOS Transistors

The total safe operating area (SOA) of LDMOS transistors is discussed. It is shown that the transistors are subjected to different kinds of stresses, yielding a combination of electrical and thermal degradation and/or failure modes. A methodology to build the total SOA for LDMOS transistors is highlighted and is experimentally verified on a 40-V LDMOS implemented in a

Hot hole degradation effects in lateral nDMOS transistors

The degradation of a n-type lateral DMOS transistor is shown to be related to the injection of hot holes in the drift region field oxide. The saturation effects observed in the parameter shifts are reproduced by a new degradation model using the bulk current as the driving force. The dependency of the hot hole injection on the layout of the LDMOS transistors is studied.

A novel hot-hole injection degradation model for lateral nDMOS transistors

For the first time, the degradation of a DMOS transistor is shown to be due to hot hole injection in the drift region field oxide. The saturation effects observed in the parameter shifts are reproduced by a new degradation model using the bulk current as the driving force. A very good agreement with experimental data is obtained for various stressing conditions.

A Comprehensive Model for Hot Carrier Degradation in LDMOS Transistors

This paper presents a comprehensive yet physical model for hot carrier degradation in LDMOS transistors. The only model input parameters are the gate and drain voltage Vds and Vgs , the internal device temperature and the device width W. The model allows calculating AC degradation performance out of the DC hot carrier data. A physical explanation of the observed effects is provided, and important differences between LDMOS and standard CMOS are highlighted

Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors

In this paper, the hot carrier degradation behaviour of a lateral nDMOS, processed in a 0.35 /spl mu/m compatible Smart Power Technology, is presented. It is shown that upon reverse bias stress, two different and competing degradation mechanisms occur. An attempt is made to identify the two mechanisms by analysis of the electrical data and by performing Charge Pumping (CP) experiments and TCAD simulations. A first mechanism is attributed to a decreased electron mobility due to increased carrier scattering upon Dit formation in the channel, whereas the second mechanism occurs in the gate overlapped drift region of the device and is due to hot-hole injection and trapping. The competition of both mechanisms depends strongly on the stress conditions. A model is presented.

I3T80: a 0.35 /spl mu/m based system-on-chip technology for 42 V battery automotive applications

This paper introduces a new modular 0.35 /spl mu/m based smart power technology which is compatible with the new 42 V battery automotive standard. The I3T80 technology offers various types of DMOS transistors in the range between 15 to 80 V. A set of bipolars, a high voltage floating diode, a large array of passive components, floating logic up to 80 V and 4 kV HBM compatible ESD protection structures are available. In addition, embedded flash memory is offered.

Development of a robust 50V 0.35 /spl mu/m based Smart Power Technology using trench isolation

This paper describes a new 0.35 /spl mu/m CMOS based smart power technology. The so-called I3T50 technology belongs to a series of intelligent interface technologies developed within AMI Semiconductor over the past years. This technology is suitable for applications up to 50 V, such as automotive, peripheral and consumer applications. Trench isolation is used to isolate the devices, substantially reducing the isolation area. The set of devices available within this technology consists of n-type and p-type CMOS and DMOS devices, bipolar transistors, a high voltage floating diode, passive components, OTP memory and a set of ESD protection structures. In the future, the technology will be extended also with a modular embedded flash memory.

XtreMOS : The First Integrated Power Transistor Breaking the Silicon Limit

Record performance of a novel power transistor integrated in a 0.35 μm power IC technology is reported. Measured specific on-state resistance of 33 mOhm*mm2 for a 94 V breakdown is breaking the silicon-limit and is the lowest reported value to date. The device outperforms its nearest rival by a factor of 2.5. The device consists of the stacking of a vertical MOS on a fully depleted vertical drift layer, leading to a high cell density

Electron trapping and interface trap generation in drain extended PMOS transistors

The hot carrier behavior of a p-type lateral drain extended MOS (DeMOS) is for the first time investigated using charge pumping (CP). In an early stage of hot carrier stress, electron injection and trapping occurs. With increasing stress time, the interface trap formation in the spacer oxide becomes the dominant mechanism. In this way, the abnormal degradation of the specific on-resistance Ron is explained.