P. Nguyen

Systematic study of the splitting kinetic of H/He co-implanted substrate

In this paper, we proposed the results of a systematic study of coimplantation of hydrogen and helium. Systematic SIMS and TEM analysis have been done.

Mechanism of the Smart Cut™ layer transfer in silicon by hydrogen and helium coimplantation in the medium dose range

We investigate the mechanism of the Si layer transfer in the Smart Cut™ technology for H and He coimplantation in the dose range of (2.5–5)×1016cm−2. Using infrared spectroscopy and cross-section transmission electron microscopy we study the microstructure of defects formed in Si in the as-implanted state. With H preimplant we observe significant enhancement of damage production as compared to the case where He is implanted first. At higher coimplant doses a buried nonuniform amorphouslike layer is formed. The structure of the layer resembles “swiss cheese” with highly damaged but still crystalline pockets embedded into amorphous material. The effect of coimplantation parameters on the thickness and crystal quality of transferred layer is discussed in the framework of a simple phenomenological model.

First demonstration of strained SiGe nanowires TFETs with ION beyond 700µA/µm

We present for the first time high performance Nanowire (NW) Tunnel FETs (TFET) obtained with a CMOS-compatible process flow featuring compressively strained Si_1-xGe_x (x=0, 0.2, 0.25) nanowires, Si_0.7Ge_0.3 Source and Drain and High-K/Metal gate. Nanowire architecture strongly improves electrostatics, while low bandgap channel (SiGe) provides increased band-to-band tunnel (BTBT) current to tackle low ON current challenges. We analyse the impact of these improvements on TFETs and compare them to MOSFET ones. Nanowire width scaling effects on TFET devices are also investigated, showing a W^-3 dependence of ON current (I_ON) per wire. The fabricated devices exhibit higher I_ON than any previously reported TFET, with values up to 760μA/μm and average subthreshold slopes (SS) of less than 80mV/dec.

The effect of order and dose of H and He sequential implantation on defect formation and evolution in silicon

In this paper we study the effect of the order and dose of H and He sequential implantation on H interaction with Si lattice defects. We use systematic infrared absorption measurements to investigate the evolution of hydrogenated point defects complexes during isothermal annealing. This analysis combined with the electron microscopy data led to the identification of the infrared absorption modes corresponding to the formation of the partially amorphized layer. The obtained results provide an important input for the optimization of the implantation conditions in order to achieve fracture in Si in the wide temperature range.

Splitting kinetics of Si0.8Ge0.2 layers implanted with H or sequentially with He and H

We have performed systematic measurements of the splitting kinetics induced by H-only and He+H sequential ion implantation into relaxed Si0.8Ge0.2 layers and compared them with the data obtained in Si. For H-only implants, Si splits faster than Si0.8Ge0.2. Sequential ion implantation leads to faster splitting kinetics than H-only in both materials and is faster in Si0.8Ge0.2 than in Si. We have performed secondary ion mass spectrometry, Rutherford backscattering spectroscopy in channeling mode, and transmission electron microscopy analyses to elucidate the physical mechanisms involved in these splitting phenomena. The data are discussed in the framework of a simple phenomenological model in which vacancies play an important role.

Experimental investigations of SiGe channels for enhancing the SGOI tunnel FETs performance

We report the fabrication and the characterization of Tunnel FETs fabricated on SiGe-On-Insulator with a High K Metal Gate (HKMG) CMOS process. The beneficial impact of low band gap SiGe channel on ID(VG) characteristics is presented and analyzed: compressive Si0.75Ge0.25 enables to increase by a factor of 20 the saturation currents, even at small gate length (LG=50nm). This large gain is due to the threshold voltage shift and to enhanced intrinsic band-to-band tunneling injection (both related to the narrow band gap of SiGe channels).

Impact of strain on access resistance in planar and nanowire CMOS devices

We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (R<inf>ACC</inf>) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on R<inf>acc</inf> (−21% for 4 V V<inf>b</inf> and −53% for −1GPa stress on pMOS FDSOI). This is in agreement with Non-Equilibrium-Green-Functions (NEGF) simulations. This RAcc(strain) dependence has been introduced into SPICE, leading to +6% increase of the RO frequency under ε<inf>n/p</inf>=0.8%/-0.5% strain, compared to the state-of-the-art model. It is thus mandatory for predictive benchmarking and optimized IC designs.

Superior performance and Hot Carrier reliability of Strained FDSOI nMOSFETs for advanced CMOS technology nodes

The Hot Carrier (HC) reliability of NMOS transistors fabricated on biaxially tensile-strain SOI substrates (sSOI) is compared to that of devices fabricated on standard unstrained SOI substrates. It is shown that sSOI-based devices not only exhibit a 10% higher performance in term of ION/IOFF but also show superior HC reliability at same drive current. This reliability improvement may be explained by a better interface quality for sSOI films.

Comparison between and oriented channels in highly strained FDSOI pMOSFETs

We fabricated highly stressed FDSOI pMOSFETs down to 15nm gate length. The impact of different stressors (CESL, raised sources and drains, STI) is studied for different device geometries and channel orientations (<;100>; or <;110>;). We evidence that pMOSFETs along <;110>; are more sensitive to stress: STI degrades narrow devices compared to wide ones whereas compressive CESL (-3GPa) and SiGe S/D improve performances (+133% mobility, +16% ION on 10μm wide devices). This makes the <;110>; orientation the most favorable channel orientation for strained pMOSFETs on planar FDSOI.