P. P. Chakrabarti

Heuristic search in restricted memory (research note)

Abstract This paper presents heuristic search algorithms which work within memory constraints. These algorithms, MA∗ (for ordinary graphs) and MAO∗ (for AND/OR graphs) guarantee admissible solutions within specified memory limitations (above the minimum required). The memory versus node expansions tradeoff is analyzed for the worst case. In the case of ordinary graphs, some experiments using the Fifteen Puzzle problem are carried out under various pruning conditions. These parameterized algorithms are found to encompass a wide class of best first search algorithms.

Reducing reexpansions in iterative-deepening search by controlling cutoff bounds

Abstract It is known that a best-first search algorithm like A∗ [5, 6] requires too much space (which often renders it unusable) and a depth-first search strategy does not guarantee an optimal cost solution. The iterative-deepening algorithm IDA∗ [4] achieves both space and cost optimality for a class of tree searching problems. However, for many other problems, it takes too much of computation time due to excessive reexpansion of nodes. This paper presents a modification of IDA∗ to an admissible iterative depth-first branch and bound algorithm IDA∗_CR for trees which overcomes this drawback of IDA∗ and operates much faster using the same amount of storage. Algorithm IDA∗_CRA, a bounded suboptimal cost variation of IDA∗_CR is also presented in order to reduce the execution time still further. Results with the 0/1 Knapsack Problem, Traveling Salesman Problem, and the Flow Shop Scheduling Problem are shown.

Design space exploration for data path synthesis

In this paper we examine the multi-criteria optimization involved in scheduling for data path synthesis (DPS). We present a method to find non-dominated schedules using a combination of restricted search and heuristic scheduling techniques. Our method supports design with architectural constraints such as the total number of functional units, buses, etc. The schedules produced have been taken to completion using GA-BIND and the results are promising.

A framework for learning in search-based systems

We provide an overall framework for learning in search based systems that are used to find optimum solutions to problems. This framework assumes that prior knowledge is available in the form of one or more heuristic functions (or features) of the problem domain. An appropriate clustering strategy is used to partition the state space into a number of classes based on the available features. The number of classes formed will depend on the resource constraints of the system. In the training phase, example problems are run using a standard admissible search algorithm. In this phase, heuristic information corresponding to each class is learned. This new information can be used in the problem solving phase by appropriate search algorithms so that subsequent problem instances can be solved more efficiently. In this framework, we also show that heuristic information of forms other than the conventional single valued underestimate value can be used, since we maintain the heuristic of each class explicitly. We show some novel search algorithms that can work with some such forms. Experimental results have been provided for some domains.

Allocation and binding in data path synthesis using a genetic algorithm approach

A technique for allocation and binding for data path synthesis (DPS) using a Genetic Algorithm (GA) approach has been developed. The proposed genetic algorithm uses a non-conventional crossover mechanism, relying on a novel force directed data path binding completion algorithm. The proposed technique has a number of features such as acceptance of some design parameters from the user, use of a bus based topology, use of multi-port memories and provision for multi-cycling and pipelining, among other features. The results obtained on the standard examples are promising.

A general best first search algorithm in AND/OR graphs

Abstract A general formulation of best first search in the setting of AND/OR graphs has been considered where both minimization and maximization occur together. This leads to the development of an AND/OR graph search algorithm called GEN-AO ∗ which works with two types of OR nodes, MIN and MAX, and uses both upper and lower bound estimates. It is shown that this algorithm generates optimal cost solutions. The worst case set of nodes expanded is examined. Such an algorithm generalizes other known algorithms. Pruning conditions for the depth-first variation is examined.

An adaptive framework for solving multiple hard problems under time constraints

We address the problem of building an integrated meta-level framework for time deliberation and parameter control for a system solving a set of hard problems. The trade-off is between the solution qualities achieved for individual problems and the global outcome under the given time-quality constraints. Each problem is modeled as an anytime optimization algorithm whose quality-time performance varies with different control parameter settings. We use the proposed meta-level strategy for generating a deliberation schedule and adaptive cooling mechanism for anytime simulated annealing (ASA) solving hard task sets. Results on task sets comprising of the traveling salesman problem (TSP) instances demonstrate the efficacy of the proposed control strategies.

Migration Aware Low Overhead ERfair Scheduler

Limiting overall scheduling overheads (primarily combining task migration overheads and task selection overheads) is of utmost importance in todays resource constrained multiprocessor real-time embedded systems because it provides premium spare processor bandwidth that may be useful in various situations. This paper presents Migration Aware Low Overhead ERfair Scheduler (MALOES), a hard real-time ERfair multiprocessor scheduler. MALOES employs a two level scheduling technique in which the outer level consists of a load balancer with an online partitioning / merging mechanism that maintains the work load mapped onto disjoint groups of processors. At the inner level, within each task-processor group a task-to processor affinity aware ERfair scheduler is used to execute tasks in ERfair manner while simultaneously attempting to minimize inter-processor task migrations. Experimental results show that MALOES incurs significantly lower overheads compared to all the known ERfair schedulers under most workload scenarios.

ERfair Scheduler with Processor Suspension for Real-Time Multiprocessor Embedded Systems

Proportional fair schedulers with their ability to provide optimal schedulability along with hard timeliness and quality-of-service guarantees on multiprocessors form an attractive alternative in real-time embedded systems that concurrently run a mix of independent applications with varying timeliness constraints. This article presents ERfair Scheduler with Suspension on Multiprocessors (ESSM), an efficient, optimal proportional fair scheduler that attempts to reduce system wide energy consumption by locally maximizing the processor suspension intervals while not sacrificing the ERfairness timing constraints of the system. The proposed technique takes advantage of higher execution rates of tasks in underloaded ERfair systems and uses a procrastination scheme to search for time points within the schedule where suspension intervals are locally maximal. Evaluation results reveal that ESSM achieves good sleep efficiency and provides up to 50% higher effective total sleep durations as compared to the Basic-ERfair scheduler on systems consisting of 2 to 20 processors.

A framework for systematic validation and debugging of pipeline simulators

Microprocessor pipeline simulation at the system level is an extremely important activity in the architecture exploration process. In this article, we address the problem of validating and debugging a pipeline simulator from the specific perspective of instruction scheduling. We propose a general framework for a systematic validation process and show that the assumptions made are justified for most standard pipeline models. The framework does not need any formal specification of the pipeline logic and hence can be readily integrated into the simulation and iteration-based architectural design space exploration process. We propose a concept of semantic equivalence between two simulations called D* equivalence which effectively captures the dataflow between instructions through registers. We then proceed to propose an algorithm which decides this equivalence in time polynomial in the number of instructions executed and the number of registers. We implement the algorithm and demonstrate how the framework facilitates debugging.