P. W. Phillips

Design and performance of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor tracker

The ABCD design is a single chip implementation of the binary readout architecture for silicon strip detectors in the ATLAS semiconductor tracker. The prototype chip has been manufactured successfully in the DMILL process. In the paper we present the design of the chip and the measurement results. The basic analogue performance of the ABCD design has been evaluated using a prototype SCT module equipped with the ABCD chips. The digital performance has been evaluated using a general purpose IC tester. The measurements confirmed that all blocks of the ABCD design are fully functional and the chips meet all basic requirements of the SCT. Wafer screening has been performed using a customised wafer tester.

The data acquisition and calibration system for the ATLAS Semiconductor Tracker

The SemiConductor Tracker (SCT) data acquisition (DAQ) system will calibrate, configure, and control the approximately six million front-end channels of the ATLAS silicon strip detector. It will provide a synchronized bunch-crossing clock to the front-end modules, communicate first-level triggers to the front-end chips, and transfer information about hit strips to the ATLAS high-level trigger system. The system has been used extensively for calibration and quality assurance during SCT barrel and endcap assembly and for performance confirmation tests after transport of the barrels and endcaps to CERN. Operating in data-taking mode, the DAQ has recorded nearly twenty million synchronously-triggered events during commissioning tests including almost a million cosmic ray triggered events. In this paper we describe the components of the data acquisition system, discuss its operation in calibration and data-taking modes and present some detector performance results from these tests

Progress in development of the readout chip for the ATLAS semiconductor tracker

The development of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS Semiconductor Tracker has entered a pre-production prototyping phase. Following evaluation of the ABCD2T prototype chip, necessary correction in the design have been implemented and the ABCD3T version has been manufactured in the DMILL process. Design issues addressed in the ABCD3T chip and performance of this pre-production prototype are discussed.

A double-sided, shield-less stave prototype for the ATLAS Upgrade strip tracker for the High Luminosity LHC

A detailed description of the integration structures for the barrel region of the silicon strips tracker of the ATLAS Phase-II upgrade for the upgrade of the Large Hadron Collider, the so-called High Luminosity LHC (HL-LHC), is presented. This paper focuses on one of the latest demonstrator prototypes recently assembled, with numerous unique features. It consists of a shortened, shield-less, and double sided stave, with two candidate power distributions implemented. Thermal and electrical performances of the prototype are presented, as well as a description of the assembly procedures and tools.

The detector control system of the ATLAS SemiConductor Tracker during macro-assembly and integration

The ATLAS SemiConductor Tracker (SCT) is one of the largest existing semiconductor detectors. It is situated between the Pixel detector and the Transition Radiation Tracker at one of the four interaction points of the Large Hadron Collider (LHC). During 2006-2007 the detector was lowered into the ATLAS cavern and installed in its final position. For the assembly, integration and commissioning phase, a complete Detector Control System (DCS) was developed to ensure the safe operation of the tracker. This included control of the individual powering of the silicon modules, a bi-phase cooling system and various types of sensors monitoring the SCT environment and the surrounding test enclosure. The DCS software architecture, performance and operational experience will be presented in the view of a validation of the DCS for the final SCT installation and operation phase.

HVMUX, the High Voltage Multiplexing for the ATLAS Tracker Upgrade

The increased luminosity of the HL-LHC will require more channels in the upgraded ATLAS Tracker, as a result of the finer detector segmentation. Thus, an upgraded and more efficient HV biasing of the sensors will also be needed and is among the many technological challenges facing the ATLAS Tracker Upgrade. A number of approaches, including the sharing of the same HV line among several sensors and suitable HV switches, along with their control circuitry are currently being investigated for this purpose. The proposed solutions along with latest test results and measurements will be described.

ATLAS strip tracker stavelets

The engineering challenges related to the supply of electrical power to future large scale detector systems are well documented. Two options remain under active study in our community, namely serial powering and the use of DC-DC converters. Whilst clearly different in detail, both have the potential to increase the efficiency of the powering system.The ATLAS Upgrade Strip Tracker Community has constructed two demonstrator stavelets using the ABCN-25 ASIC, each comprising four silicon strip detector modules. The first stavelet is serially powered, using shunt transistors integrated into the ABCN-25 chip to maintain the required operating voltage given a constant supply current, and the second stavelet uses STV-10 DC-DC converters provided by the CERN group. Although the detailed test programme shall continue at CERN, results from stavelet tests made at RAL are presented here.

A double-sided silicon micro-strip Super-Module for the ATLAS Inner Detector upgrade in the High-Luminosity LHC

The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several years of successful data-taking, the LHC physics programme will be extended in the so-called High-Luminosity LHC, where the instantaneous luminosity will be increased up to 5 × 1034 cm−2 s−1. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as the existing detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip detectors at intermediate and outer radii. The super-module is an integration concept proposed for the strip region of the future ATLAS tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local support structure. An electrical super-module prototype for eight double-sided strip modules has been constructed. The aim is to exercise the multi-module readout chain and to investigate the noise performance of such a system. In this paper, the main components of the current super-module prototype are described and its electrical performance is presented in detail.

The ATLAS Detector Control System

The ATLAS experiment is one of the multi-purpose experiments at the Large Hadron Collider (LHC) at CERN, constructed to study elementary particle interactions in collisions of high-energy proton beams. Twelve different sub detectors as well as the common experimental infrastructure are controlled and monitored by the Detector Control System (DCS) using a highly distributed system of 140 server machines running the industrial SCADA product PVSS. Higher level control system layers allow for automatic control procedures, efficient error recognition and handling, manage the communication with external systems such as the LHC controls, and provide a synchronization mechanism with the ATLAS data acquisition system. Different databases are used to store the online parameters of the experiment, replicate a subset used for physics reconstruction, and store the configuration parameters of the systems. This contribution describes the computing architecture and software tools to handle this complex and highly interconnected control system.

The ATLAS SCT grounding and shielding concept and implementation

This paper describes the design and implementation of the grounding and shielding system for the ATLAS SemiConductor Tracker (SCT). The mitigation of electromagnetic interference and noise pickup through power lines is the critical design goal as they have the potential to jeopardize the electrical performance. We accomplish this by adhering to the ATLAS grounding rules, by avoiding ground loops and isolating the different subdetectors. Noise sources are identified and design rules to protect the SCT against them are described. A rigorous implementation of the design was crucial to achieve the required performance. This paper highlights the location, connection and assembly of the different components that affect the grounding and shielding system: cables, filters, cooling pipes, shielding enclosure, power supplies and others. Special care is taken with the electrical properties of materials and joints. The monitoring of the grounding system during the installation period is also discussed. Finally, after connecting more than four thousand SCT modules to all of their services, electrical, mechanical and thermal within the wider ATLAS experimental environment, dedicated tests show that noise pickup is minimised.