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Customized Exposed Datapath Soft-Core Design Flow with Compiler Support

A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with accompanying software development tools. However, a common shortcoming with the current soft-core offerings is their limited software execution capability: the required performance for the implementation can be often reached only with instruction set extensions. In this paper, we propose and evaluate an application-specific processor design toolset that uses a multi-issue exposed data path processor architecture template. The main benefit of the architecture is scalability with respect to instruction-level parallelism (ILP). The design flow allows the designer to freely customize the data path resources in the core to exploit the ILP available in computation intensive kernels. The design toolset includes a retargetable C compiler and an architecture simulator, making design space exploration feasible. The experiments show that a relatively small soft-core tailored with the toolset provides significant speedups on software execution without using any instruction set extensions. The best measured speedup in comparison to the major commercial soft-cores was fourfold in applications from the CHStone benchmark suite, while the amount of consumed FPGA resources remained moderate.

OpenCL-based design methodology for application-specific processors

OpenCL is a programming language standard which enables the programmer to express the application by structuring its computation as kernels. The OpenCL compiler is given the explicit freedom to parallelize the execution of kernel instances at all the levels of parallelism. In comparison to the traditional C programming language which is sequential in nature, OpenCL enables higher utilization of parallelism naturally available in hardware constructs while still having a feasible learning curve for engineers familiar with the C language. This paper describes methodology and compiler techniques involved in applying OpenCL as an input language for a design flow of application-specific processors. At the core of the methodology is a whole program optimizing compiler that links together the host and kernel codes of the input OpenCL program and parallelizes the result on a customized statically scheduled processor. The OpenCL vendor extension mechanism is used to provide clean access to custom operations. The methodology is studied with a design case to verify the scalability of the implementation at the instruction level and to exemplify the use of custom operations. The case shows that the use of OpenCL allows producing scalable application-specific processor designs and makes it possible to gradually reach the performance of hand-tailored RTL designs by exploiting the OpenCL extension mechanism to access custom hardware operations of varying complexity.

Platform based on open-source cores for industrial applications

The latest version of the international technology roadmap for semiconductors predicts that design reuse will be essential in the near future to face the constantly increasing design complexity. The concept comes from software engineering in which reuse is a fundamental technology. In order to provide libraries and applications to reuse in software development, some open-source initiatives (e.g. Linux, gcc, X, mysql) have appeared during the last decades. The basic idea is to distribute the library or application source code (normally free-of-charge) and allow any developer to use, modify, debug and improve it. Several initiatives have tried to port this idea to hardware development. The main goal of this paper is to develop a synthesizable platform described in SystemC from an open architecture. The platform includes a CPU (OpenRISC) and some basic peripherals. A set of software development tools (compiler, assembler, debugger) and RTOS (eCos) has also been developed. This work enables the evaluation of the advantages and disadvantages of the open-source model in electronic system design.

Operating System for Symmetric Multiprocessors on FPGA

Soft-core based multiprocessor systems are getting very popular in the FPGA design world. There are many computer architectures that has been used for building multiprocessor systems on FPGAs, including SMP (symmetric multiprocessor). One of the main drawback of this SMP systems is the unavailability of operating systems that allow programming multi-threaded applications that make good use of the multiple processors of the system. This paper details an operating system designed to be used with SMP systems based on the MicroBlaze soft-core processor. The OS is tested with three different applications on an SMP system which implements all the software and hardware required for the OS to work on different SMP systems.

Secure IP downloading for SRAM FPGAs

Nowadays there is a growing number of systems based on FPGAs spread over wide areas. When these kind of systems are used, serious security problems may appear. The configuration data for these devices can be very sensitive information that has to be protected against piracy and reverse engineering. In this paper, the main target is to describe a rapid prototyping platform that allows Secure IP downloading and Rights Management. This platform is based on the possibility offered by the new FPGA families for reprogramming part of the device while the rest is working. This work shows how an FPGA system based on an Open Source OpenRISC 1200 microprocessor takes advantage of this feature to perform the Secure Download of the software and the hardware needed to run a User Application. The platform includes digital signature schemes, symmetric encryption and hashing functions to increment the security. An IP rights management method using this architecture is also presented.

Genetic Algorithm for Boolean minimization in an FPGA cluster

Evolutionary algorithms are an alternative option to the Boolean synthesis due to that they allow one to create hardware structures that would not be able to be obtained with other techniques. This paper shows a parallel genetic programming (PGP) Boolean synthesis implementation based on a cluster of FPGAs that takes full advantage of parallel programming and hardware/software co-design techniques. The performance of our cluster of FPGAs implementation has been compared with an HPC implementation. The experimental results have shown an excellent behavior in terms of speed up (up to ×500) and in terms of solving the scalability problems of this algorithms present in previous works.

Exploring FPGA Capabilities for Building Symmetric Multiprocessor Systems

Advances in FPGA technologies allow designing highly complex systems using on-chip FPGA resources and intellectual property (IP) cores. Furthermore, it is possible to build multiprocessor systems using hard-core or soft-core processors increasing the range of applications that can be implemented on an FPGA. This paper presents an implementation of a symmetric multiprocessor (SMP) system on an FPGA using a vendor provided soft-core processor and a new set of software libraries specially developed for writing applications for this kind of systems. Experimental results show how this approach can improve performance of parallelizable software applications.

A Self-Reconfigurable Multimedia Player on FPGA

With the hype of multimedia devices, many different audio and video formats have appeared in recent years. The sales of portable multimedia players like Apples ipod have also experiment and incredible growth. These devices are usually based on general purpose microprocessors and, when a new audio or video format appears, a software upgrade is needed or, in the worst case, the new format will not be supported by the player. This work presents a novel implementation where an FPGA based multimedia player makes use of the self-reconfiguration capabilities of modern FPGA families in order to support new multimedia formats. When the player needs to play a song with a non-supported format it securely downloads the required hardware from Internet and reprograms the FPGA with the new codec

Hardware accelerated montecarlo financial simulation over low cost FPGA cluster

The use of computational systems to help making the right investment decisions in financial markets is an open research field where multiple efforts have being carried out during the last few years. The ability of improving the assessment process and being faster than the rest of the players is one of the keys for the success on this competitive scenario. This paper explores different options to accelerate the computation of the option pricing problem (supercomputer, FPGA cluster or GPU) using the Montecarlo method to solve the Black-Scholes formula, and presents a quantitative study of their performance and scalability.

Self-reconfigurable secure file system for embedded Linux

With the growth of the portable electronic devices market, not only the protection of the data for the users but also the security of the designs themselves has grown significantly in importance. A solution is presented where a Linux kernel running on a PowerPC processor included in the Virtex-II Pro FPGA family is upgraded to support hardware acceleration on the ciphering tasks. In this way all the programs running on the PPC that make use of the Linux CryptoAPI can be accelerated by hardware in a transparent way without having the programmer to rewrite the applications. To provide more flexibility, the FPGAs self-reconfiguration capability can be used to reprogram any cryptographic algorithm demanded by the Linux CryptoAPI by just including a new software driver for the operating system, thus allowing the internal configuration access port (ICAP) of the FPGA to manage any cryptographic coprocessor at any time. The approach is validated on a real application using the Linux CryptoAPI: a ciphered file system that stores the system data in a secured way.