Pai Yu Chen

Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect

The crossbar array architecture with resistive synaptic devices is attractive for on-chip implementation of weighted sum and weight update in the neuro-inspired learning algorithms. This paper discusses the design challenges on scaling up the array size due to non-ideal device properties and array parasitics. Circuit-level mitigation strategies have been proposed to minimize the learning accuracy loss in a large array. This paper also discusses the peripheral circuits design considerations for the neuro-inspired architecture. Finally, a circuit-level macro simulator is developed to explore the design trade-offs and evaluate the overhead of the proposed mitigation strategies as well as project the scaling trend of the neuro-inspired architecture.

Emerging Memory Technologies: Recent Trends and Prospects

This tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STTMRAM), phase-change random access memory (PCRAM), and resistive random access memory (RRAM). Emerging NVM cell characteristics are summarized, and device-level engineering trends are discussed. Emerging NVM array architectures are introduced, including the one-transistor-one-resistor (1T1R) array and the cross-point array with selectors. Design challenges such as scaling the write current and minimizing the sneak path current in cross-point array are analyzed. Recent progress on megabit-to gigabit-level prototype chip demonstrations is summarized. Finally, the prospective applications of emerging NVM are discussed, ranging from the last-level cache to the storage-class memory in the memory hierarchy. Topics of three-dimensional (3D) integration and radiation-hard NVM are discussed. Novel applications beyond the conventional memory applications are also surveyed, including physical unclonable function for hardware security, reconfigurable routing switch for field-programmable gate array (FPGA), logic-in-memory and nonvolatile cache/register/flip-flop for nonvolatile processor, and synaptic device for neuro-inspired computing.

Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design

In this paper, we present a compact model for metal-oxide-based resistive random access memory (RRAM) devices with bipolar switching characteristics. The switching mechanism relies on the dynamics of conductive filament growth/dissolution in the oxide layer. Besides the dc and pulsed I-V characteristics, the model also captures the RRAM retention property and the temperature dynamics. The model parameters and the device variations are calibrated from the experimental data of IMEC HfOx-based RRAM devices. The model has been implemented in Verilog-A, which can be easily adapted into the SPICE simulator for the circuit-level analysis. As case studies, we demonstrate the models applications on the programming scheme design of the 1-transistor-1-resistor array, as well as the design space exploration of the 1-selector-1-resistor cross-point array toward megabit-level.

Exploiting resistive cross-point array for compact design of physical unclonable function

This work presents the optimized design of a physical unclonable function (PUF) primitive based on the cross-point resistive random access memory (RRAM) array. The randomness of the PUF comes from the resistance variation of RRAM cells in the array. A four-cell selection scheme is proposed to create a large number of challenge-response pairs necessary for achieving a high security level. To analyze the performance of the PUF with respect to uniqueness and reliability, the RRAM cross-point array is fabricated and the device parameters are calibrated from the experimental data. Our study shows that the RRAM PUF can function properly across a wide temperature range without degradation in the performance. However, IR drop due to the interconnect resistance in the array can potentially hamper the performance. To mitigate the effect of IR drop, a reverse scaling rule on the feature size (F) is proposed for RRAM PUF. While this increases the area of the RRAM PUF, it improves the PUF performance significantly. Compared to a conventional SRAM PUF in 45nm node, a RRAM PUF array size of 1024×1024 with relaxed F=200nm has -45% lower area, while offering better robustness against invasive and side-channel attacks.

Programming Protocol Optimization for Analog Weight Tuning in Resistive Memories

Analog weight tuning in resistive memories is attractive for multilevel operation and neuro-inspired computing. To tune the device conductance to the desired states as fast as possible without sacrificing the accuracy, we propose an optimization programming protocol by adjusting the pulse amplitude incremental steps, the pulsewidth incremental steps, and the start voltages. Our experimental results on HfOx-based resistive memories indicate that avoiding over-reset by appropriate programming parameters is critical for fast convergence of the conductance tuning. The over-reset behavior is caused by the stochastic nature of filament formation and rupture, as simulated by a 1-D filament model.

Binary neural network with 16 Mb RRAM macro chip for classification and online training

On-chip implementation of large-scale neural networks with emerging synaptic devices is attractive but challenging, primarily due to the pre-mature analog properties of todays resistive memory technologies. This work aims to realize a large-scale neural network using todays available binary RRAM devices for image recognition. We propose a methodology to binarize the neural network parameters with a goal of reducing the precision of weights and neurons to 1-bit for classification and <8-bit for online training. We experimentally demonstrate the binary neural network (BNN) on Tsinghuas 16 Mb RRAM macro chip fabricated in 130 nm CMOS process. Even under finite bit yield and endurance cycles, the system performance on MNIST handwritten digit dataset achieves ∼96.5% accuracy for both classification and online training, close to ∼97% accuracy by the ideal software implementation. This work reports the largest scale of the synaptic arrays and achieved the highest accuracy so far.

MNSIM: Simulation platform for memristor-based neuromorphic computing system

Memristor-based neuromorphic computing system provides a promising solution to significantly boost the power efficiency of computing system. Memristor-based neuromorphic computing system has a wide range of design choices, such as the various memristor crossbar cell designs and different parallelism degrees of peripheral circuits. However, a memristor-based neuromorphic computing system simulator, which is able to model the system and realize an early-stage design space exploration, is still missing. In this paper, we develop a memristor-based neuromorphic system simulation platform (MNSIM). MNSIM proposes a general hierarchical structure for memristor-based neuromophic computing system, and provides flexible interface for users to customize the design. MNSIM also provides a detailed reference design for large-scale applications. MNSIM embeds estimation models of area, power, and latency to simulate the performance of system. To estimate the computing accuracy, MNSIM proposes a behavior-level model between computing error rate and crossbar design parameters considering the influence of interconnect lines and non-ideal device factors. The error rate between our accuracy model and SPICE simulation result is less than 1%. Experimental results show that MNSIM achieves more than 7000 times speed-up compared with SPICE and obtains reasonable accuracy. MNSIM can further estimate the trade-off between computing accuracy, energy, latency, and area among different designs for optimization.

Physical Unclonable Function Exploiting Sneak Paths in Resistive Cross-point Array

The physical unclonable function (PUF) is a promising innovative hardware security primitive that leverages the inherent randomness in the physical systems to produce unique responses upon the inquiry of challenges, thus the PUF could serve as a fingerprint for device authentication. In this paper, we propose a novel PUF implementation exploiting the sneak paths in the resistive cross-point (X-point) array, as a hardware security primitive. The entanglement of the sneak paths in the X-point array greatly enhances the entropy of the physical system, thereby increasing the space of challenge-response pairs to make a strong PUF. The X-point PUF characteristics, such as uniqueness and reliability, are experimentally evaluated on the fabricated 12 × 12 cross-point arrays based on the Pt/HfOx/TiN structure. The measurement results show that the average inter-Hamming distance of the response bits is around 46.2% across 28 different arrays, showing sufficient uniqueness. The measurement results also demonstrate that 0% intra-Hamming distance (or 100% reliability) of the response bits can be maintained more than 7.2 h at 100 °C (or equivalently ten years at 40 °C). This paper demonstrates the feasibility of using X-point PUF as a lightweight and reliable PUF for device authentication.

Architecting 3D vertical resistive memory for next-generation storage systems

Resistive Random Access Memory (ReRAM) has several advantages over current NAND Flash technology, highlighting orders of magnitude lower access latency and higher endurance. Recently proposed 3D vertical cross-point ReRAM (3D-VRAM) architecture is an encouraging development in ReRAMs evolution as a cost-competitive solution, and thus attracts a lot of attention in both industry and academia. In this work, an array-level model to estimate the read/write energy and characterize the vertical access transistor is developed. We use the model to study a range of design trade-offs by tuning the cell-level characteristics and the read/write schemes. The design space exploration addresses several critical issues that are either unique to 3D-VRAM or have substantially different concerns from the 2D cross-point array design. It provides insights on the design optimizations of the array density and access energy, and several important conclusions have been reached. Then we propose multi-directional write driver to mitigate the writer circuitry overhead, and use remote sensing scheme to take full advantage of limited on-die sensing resources. The benefits of these optimizations are evaluated and validated in our macro-architecture model. With trace-based simulations, system-level comparisons between 3D-VRAM and a wide spectrum of memories are performed in mixed aspects of performance, cost, and energy. The results show that our optimized 3D-VRAM design are better than other contenders for storage memory in both performance and energy.

Demonstration of Convolution Kernel Operation on Resistive Cross-Point Array

Convolution is the key operation in the convolutional neural network, one of the most popular deep learning algorithms. The implementation of the convolution kernel on the resistive cross-point array is different than the implementation of the matrix-vector multiplication in prior works. In this letter, we propose a dimensional reduction of 2-D kernel matrix into 1-D column vector, i.e., a column of the array, and enable the parallel readout of multiple 2-D kernels simultaneously. As a proof-of-concept demonstration, we use the Prewitt kernels to detect both horizontal and vertical edges of the 20 × 20 pixels of black and-white MNIST handwritten digits. The experiments were performed on the fabricated 12 × 12 resistive cross-point array based on the Pt/HfOx/TiN structure. The experimental results of the Prewitt kernel operation perfectly matches the simulation results, indicating the feasibility of the proposed implementation methodology of the convolution kernel on resistive cross-point array.