Palmer Wright Agnew

Microprocessor implementation of mainframe processors by means of architecture partitioning

The benefits of Large-Scale Integration (LSI) implementations have applied quite naturally to processors with relatively low performances and simple architectures; e.g., the one-chip microprocessors used in personal computers contain several thousand logic gates. Mainframe processors, however, have so far been limited to using logic chips that contain several hundred logic gates. The best use of LSI logic employs microprocessors to keep critical paths on chip, thus keeping pin counts and power dissipations within reasonable limits. Microprocessors have been extensively used to implement peripheral functions, such as I/O device control. However, as of this writing, a single state-of-the-art microprocessor cannot contain a mainframe processor function. Therefore, new machine organizations are needed to use todays state-of-the-art microprocessors to implement a mainframe processor. This paper examinesse veral methods for applying LSI and microprocessors to the design of processors of increasing performance and complexity, and describes a number of specific approaches to microprocessor-based LSI implementation of System/370 processors. The most successful approaches partition the System/370 instruction set into subsets, each of which can be implemented by microcode on a special microprocessor or by programs written for an off-the-shelf microprocessor.