Paolo Zicari

SAD-Based Stereo Matching Circuit for FPGAs

This paper presents a novel FPGA-based stereo matching system. The proposed circuit operates on 512times512 stereo images with a maximum disparity of 255. It achieves a 286 MHz running frequency and a frame rate of 25.6 f/s.

Low-power split-path data-driven dynamic logic

Data-pre-charged dynamic logic, also known as data-driven dynamic logic (D3L), is very efficient when low-power constraints are mandatory. Differently from conventional dynamic domino logic, which exploits a clock signal, D3L uses a subset of the input data signals for pre-charging the dynamic node, thus avoiding the clock distribution network. Power consumption is significantly reduced, but the pre-charge propagation path delay affects the speed performances and limits the energy-delay product (EDP) improvements. This study presents a new dynamic logic named split-path D3L (SPD3L) that overcomes the speed limitations of D3L. When applied to a 16 times 16 bit booth multiplier realised with STMicroelectronics 65 nm IV CMOS technology, the proposed technique leads to an EDP 25 and 30% lower than standard dynamic domino logic and conventional D3L counterparts, respectively.

Designing High-Speed Adders in Power-Constrained Environments

Data-driven dynamic logic (D3L) is very efficient when low-power constraints are mandatory. Unfortunately, this advantage is typically obtained at the expense of speed performances. This paper presents a novel technique to realize D3L parallel prefix tree adders without significantly compromising speed performance. When applied to a 64-bit Kogge-Stone adder realized with 90-nm complementary metal-oxide-semiconductor (CMOS) technology, the proposed technique leads to an energy-delay product that is 29% and 21% lower than its standard domino logic and conventional D3L counterparts, respectively. It also shows a worst case delay that is 10% lower than that of the D3L approach and only 5% higher than that of the conventional domino logic.

A fast carry chain adder for Virtex-5 FPGAs

This paper proposes a fast adder structure for Xilinx Virtex-5 FPGAs. The generic n-bit adder is split into two n/2-bit adders. The portion which computes the n/2 most significant sum bits receives the carry input signal from a purpose-designed fast carry generator instead of the n/2-bit adder generating the least significant sum bits. This allows outperforming the ripple carry adders implemented in the chosen FPGA family. The fast carry chain propagation is reached by optimizing the use of 6-input LUTs together with the dedicated MUXCY resources available in the Virtex-5 FPGA chip. A 64-bit adder designed as proposed here is ∼11% and ∼35% faster than the standard carry chain adder and the DSP-based adder implementation, respectively.

Low-cost FPGA stereo vision system for real time disparity maps calculation

Several applications demand efficient hardware implementations of stereo vision systems in order to furnish real time three-dimensional measurements. This paper proposes a complete fast low-cost stereo vision system that performs stereo image rectification with tangential and radial distortion removal, computes dense disparity maps using the Sum of Absolute Differences as the dissimilarity metric, and, finally, exploits a novel injective consistency check purpose-designed for eliminating unreliable disparity values. The proposed system has been realized and hardware tested for several images resolutions and disparity ranges. When 1280x720 grayscale images are processed with the disparity range equal to 30, the system allows a frame rate up to 97fps@89MHz to be reached. It has been realized on a single low-cost XilinxVirtex-4 XC4VLX60 FPGA chip and it occupies 63 DSPs, 128 BRAMs and 15728 slices.

A matrix product accelerator for field programmable systems on chip

This paper presents a novel architecture for matrix multiplication optimized to be integrated as a coprocessor unit with embedded processors in modern FPGAs. In contrast with previous proposals that accelerate just the matrix multiplication computation, the coprocessor here proposed has been purposely designed to exploit an efficient communication protocol for the data exchange between it and the host processor that significantly reduces the whole computational time. The complete system formed by a 32-bit RISC processor augmented by the proposed coprocessor unit has been hardware implemented. Such system can be easily used to accelerate matrix multiplication with virtually any matrix sizes. Simulation tests and measurements demonstrate that the system requires a number of clock cycles more than halved, with respect to competitive solutions.

Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications

This article presents a novel configuration scrubbing core, used for internal detection and correction of radiation-induced configuration single and multiple bit errors, without requiring external scrubbing. The proposed technique combines the benefits of fast radiation-induced fault detection with fast restoration of the device functionality and small area and power overheads. Experimental results demonstrate that the novel approach significantly improves the availability in hostile radiation environments of FPGA-based designs. When implemented using a Xilinx XC2V1000 Virtex-II device, the presented technique detects and corrects single bit upsets and double, triple and quadruple multi bit upsets, occupying just 1488 slices and dissipating less than 30 mW at a 50MHz running frequency.

An optimized adder accumulator for high speed MACs

A novel architecture of adder with accumulation register here called adder accumulator (AAC) is presented. When used for the implementation of a MAC, it drastically reduces the delay of the final adder portion with a very small extra area consumption. The novel architecture merges the adder block and the accumulator register present in the MAC operator furnishing the possibility to use two separate n/2 bit adders instead of the n bit adder generally employed to accumulate the n bit MAC result

A self-hosting configuration management system to mitigate the impact of Radiation-Induced Multi-Bit Upsets in SRAM-based FPGAs

This paper presents an efficient circuit to mitigate the impact of Radiation-Induced Multi-Bit Upsets in Xilinx FPGAs from Virtex-II on. The proposed internal scrubber detects and corrects single bit upsets and double, triple and quadruple multi bit upsets by efficiently exploiting permuted and compressed Hamming check codes. When implemented using a Xilinx XC2V1000 Virtex-II device, it occupies just 1488 slices and dissipates less than 30 mW at a 50MHz running frequency, taking just 18us to complete the error checking over a single frame, and 18.76us to repair the corrupted frame.

An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications

This paper presents an efficient approach to protect an FPGA design against Single Event Upsets (SEUs). A novel configuration scrubbing core, instantiated at the top level of the user project, is used for internal detection and correction of SEU-induced configuration errors without requiring further external radiation hardened control hardware. As demonstrated in the paper, this approach combines the benefits of fast SEU faults detection with fast restoration of the device functionality and small overhead. Moreover, the proposed technique result highly versatile and can be adopted for different FPGA device families.