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Dive into the research topics where Paritosh K. Pandya is active.

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Featured researches published by Paritosh K. Pandya.


Archive | 2004

FST TCS 2003: Foundations of Software Technology and Theoretical Computer Science

Paritosh K. Pandya; M. Agrawal; Jaikumar Radhakrishnan

Contributed Papers.- A Cryptographically Sound Security Proof of the Needham-Schroeder-Lowe Public-Key Protocol.- Constructions of Sparse Asymmetric Connectors.- A Separation Logic for Resource Distribution.- An Equational Theory for Transactions.- Axioms for Regular Words.- 1-Bounded TWA Cannot Be Determinized.- Reachability Analysis of Process Rewrite Systems.- Pushdown Games with Unboundedness and Regular Conditions.- Real-Time Model-Checking: Parameters Everywhere.- The Caucal Hierarchy of Infinite Graphs in Terms of Logic and Higher-Order Pushdown Automata.- Deciding the Security of Protocols with Diffie-Hellman Exponentiation and Products in Exponents.- Subtyping Constraints in Quasi-lattices.- An Improved Approximation Scheme for Computing Arrow-Debreu Prices for the Linear Case.- Word Equations over Graph Products.- Analysis and Experimental Evaluation of a Simple Algorithm for Collaborative Filtering in Planted Partition Models.- Comparing Sequences with Segment Rearrangements.- On Logically Defined Recognizable Tree Languages.- Randomized Time-Space Tradeoffs for Directed Graph Connectivity.- Distance-Preserving Approximations of Polygonal Paths.- Joint Separation of Geometric Clusters and the Extreme Irregularities of Regular Polyhedra.- On the Covering Steiner Problem.- Minimality Results for the Spatial Logics.- Algorithms for Non-uniform Size Data Placement on Parallel Disks.- Efficient Algorithms for Abelian Group Isomorphism and Related Problems.- Quasi-polynomial Time Approximation Algorithm for Low-Degree Minimum-Cost Steiner Trees.- Model Checking and Satisfiability for Sabotage Modal Logic.- Merging and Sorting By Strip Moves.- The Macro Tree Transducer Hierarchy Collapses for Functions of Linear Size Increase.- Distributed Games.- Maintenance of Multidimensional Histograms.- Tagging Makes Secrecy Decidable with Unbounded Nonces as Well.- Quantum and Classical Complexity Classes: Separations, Collapses, and Closure Properties.- On the Greedy Superstring Conjecture.- Invited Papers.- Reasoning about Infinite State Systems Using Boolean Methods.- Stringent Relativization.- Component-Based Construction of Deadlock-Free Systems.- Moderately Hard Functions: From Complexity to Spam Fighting.- Zigzag Products, Expander Constructions, Connections, and Applications.


availability, reliability and security | 2006

Timed modelling and analysis in Web service compositions

Raman Kazhamiakin; Paritosh K. Pandya; Marco Pistore

In this paper we present an approach for modelling and analyzing time-related properties of Web service compositions defined as a set of BPEL4WS processes. We introduce a formalism, called Web service timed state transition systems (WSTTS), to capture the timed behavior of the composite Web services. We also exploit an interval temporal logic to express complex timed assumptions and requirements on the systems behavior. Building upon of this formalization, we provide techniques and tools for model checking BPEL4WS compositions against time-related requirements. We perform a preliminary experimental evaluation of our approach and tools with the help of the e-government case study.


Distributed Computing | 1991

P-A logic: a compositional proof system for distributed programs

Paritosh K. Pandya; Mathai Joseph

SummaryThis paper describes a compositional proof system called P-A logic for establishing weak total correctness and weak divergence correctness of CSP-like distributed programs with synchronous and asynchronous communication. Each process in a network is specified using logical assertions in terms of a presuppositionPre and an affirmationAff as a triple {Pre}S{Aff}. For purely sequential programs, these triples reduce to the familiar Hoare triples. In distributed programs, P-A triples allow the behaviour of a process to be specified in the context of assumptions about its communications with the other processes in the network. Safety properties of process communications, and progress properties such as finiteness and freedom from divergence can be proved. An extension of P-A logic allowing proof of deadlock freedom is outlined. Finally, proof rules for deriving some liveness properties of a program from its P-A logic specification are discussed; these properties have the form “Q untilR”, whereQ, R are assertions over communication traces. Other liveness properties may be derived from these properties using the rules of temporal logic.


international conference on web services | 2006

Representation, Verification, and Computation of Timed Properties in Web

Raman Kazhamiakin; Paritosh K. Pandya; Marco Pistore

In this paper we address the problem of qualitative and quantitative analysis of timing aspects of Web service compositions defined as a set of BPEL4WS processes. We introduce a formalism, called Web service timed state transition systems (WSTTS), to capture the timed behavior of the composite Web services. We also exploit an interval temporal logic to express complex timed assumptions and requirements on the systems behavior. Building on top of this formalization, we provide techniques and tools for model-checking BPEL4WS compositions against time-related requirements. We also present a symbolic algorithm that can be used to compute duration bounds of behavioral intervals that satisfy such requirements. We perform a preliminary experimental evaluation of our approach and tools with the help of an e-Government case study


Lecture Notes in Computer Science | 1998

Duration Calculus of Weakly Monotonic Time

Paritosh K. Pandya; Dang Van Hung

We extend Duration Calculus to a logic which allows description of Discrete Processes where several steps of computation can occur at the same time point. The resulting logic is called Duration Calculus of Weakly Monotonic Time (WDC). It allows effects such as true synchrony and digitisation to be modelled. As an example of this, we formulate a novel semantics of Timed CSP assuming that the communication and computation take no time.


Theoretical Computer Science - Special issue on hybrid systems archive | 1995

Finite divergence

Michael R. Hansen; Paritosh K. Pandya; Zhou Chaochen

Real-time and hybrid systems have been studied so far under the assumption of finite variability. In this paper, we consider models in which systems exhibiting finite divergence can also be analysed. In such systems the state of the system can change infinitely often in a finite time. This kind of behaviour arises in many representations of hybrid systems, and also in theories of nonlinear systems. The aim, here, is to provide a theory where pathological behaviour such as finite divergence can be analysed if only to pvoue that it does not occur in systems of interest. Finite divergence is studied using the framework of duration calculus. Axioms and proof rules are given. Patterns of occurrence of divergence are classified into dense divergence, accumulative divergence and discrete divergence by appropriate axioms. Induction rules are given for reasoning about discrete divergence.


tools and algorithms for construction and analysis of systems | 2001

Model Checking CTL*[DC]

Paritosh K. Pandya

We define a logic called CTL*[DC] which extends CTL* with ability to specify past-time and quantitative timing properties using the formulae of Quantified Discrete-time Duration Calculus (QDDC). Alternately, we can consider CTL*[DC] as extending logic QDDC with branching and liveness.As our main result, we show a reduction of CTL*[DC] model checking problem to model checking of CTL* formulae. The reduction relies upon an automata-theoretic decision procedure for QDDC. Moreover, it preserves the subsets CTL and LTL of CTL*. The reduction is of practical relevance as model checking of CTL* as well as its subsets CTL and LTL are well studied and even implemented into a number of tools. We briefly discuss an implementation of a model checking tool for CTL[DC] called CTLDC, based on the above theory. CTLDC can model check SMV, Verilog and Esterel designs using tools SMV, VIS and Xeve, respectively.


Electronic Notes in Theoretical Computer Science | 2002

Interval Duration Logic: Expressiveness and Decidability

Paritosh K. Pandya

Abstract We investigate a variant of dense-time Duration Calculus which permits model checking using timed/hybrid automata. We define a variant of the Duration Calculus, called Interval Duration Logic, ( IDL ), whose models are timed state sequences [1]. A subset LIDL of IDL consisting only of located time constraints is presented. As our main result, we show that the models of an LIDL formula can be captured as timed state sequences accepted by an event-recording integrator automaton. A tool called IDLVALID for reducing LIDL formulae to integrator automata is briefly described. Finally, it is shown that LIDL has precisely the expressive power of event-recording integrator automata, and that a further subset LIDL - corresponds exactly to event-recording timed automata [2]. This gives us an automata-theoretic decision procedure for the satisfiability of LIDL – formulae.


computer aided verification | 2003

Digitizing Interval Duration Logic

Gaurav Chakravorty; Paritosh K. Pandya

In this paper, we study the verification of dense time properties by discrete time analysis. Interval Duration Logic, (IDL), is a highly expressive dense time logic for specifying properties of real-time systems. Validity checking of IDL formulae is in general undecidable. A corresponding discrete-time logic QDDC has decidable validity.


IFIP TCS | 2008

Marking the chops: an unambiguous temporal logic

Kamal Lodaya; Paritosh K. Pandya; Simoni S. Shah

Interval Temporal Logic [11] is a highly expressive and succinct logic whose satisfiability over finite words is non-elementary in the number of alternations of chop and negation operators. All the sublogics of ITL with elementary decidability known to us restrict this alternation depth. In this paper, we define a sublogic of Interval Temporal Logic by replacing chops with marked chops but without any restriction on the alternation depth. We show that the resulting logic admits unique parsing of a word matching a formula, with the consequence that membership is in LOGDCFL and satisfiability is in PSPACE. As our first result, we give an effective model-preserving reduction from UITL to the partially ordered two-way deterministic finite automata of Schwentick, Therien and Vollmer [14]. We show that the size of the resulting automaton is quadratic in the size of the formula. We also have an exponential converse reduction from po2dfa to UITL. It follows from the work of Schutzenberger [13], Therien and Wilke [19] that this unambiguous ITL has same expressive power as the first-order logic with two variables [10].

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Shankara Narayanan Krishna

Indian Institute of Technology Bombay

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Khushraj Madnani

Indian Institute of Technology Bombay

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Simoni S. Shah

Tata Institute of Fundamental Research

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P. Vijay Suman

Tata Institute of Fundamental Research

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K. Narayan Kumar

Chennai Mathematical Institute

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Mathai Joseph

Tata Institute of Fundamental Research

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Dang Van Hung

United Nations University International Institute for Software Technology

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Marco Pistore

fondazione bruno kessler

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