Parminder Ghuman

Parallel VLSI equalizer architectures for multi-Gbps satellite communications

This paper provides an overview of a new VLSI architecture for implementing a frequency domain LMS complex equalizer. The architecture incorporates a simple sub-convolution method, digital vector processing, specialized FFT-IFFT hardware architectures, and the DFT-IDFT overlap-and-save filter method. A key property of the new architecture is that the equalizer tap length may be chosen completely independently of the FFT-IFFT lengths and input data block lengths. Theoretically unlimited tap lengths are possible with short FFT-IFFT pairs. It is demonstrated that the new parallel architecture is very well suited for processing multi-Gbps digital communication data rates with relatively low speed CMOS hardware. The presented VLSI equalizer architecture processes complex demodulated symbols at 1/4 the symbol rate. The parallel equalizer, operating on one sample per symbol, has 32 coefficients, is decision directed and processes data modulated with QPSK and 16QAM. The equalizer is integrated into the 2.4 Gbps all-digital wireless parallel demodulator ASIC. The receiver is currently being developed by JPL/CalTech and NASAs Goddard Space Flight Center. This parallel all-digital receiver designed for satellite communications operates at 1/16 the analog-to-digital sample rate. Finally, a complexity comparison between this equalizer architecture and the traditional frequency domain fast LMS equalizer is given.

Reliable, Low Cost All-Digital Receiver

The current receiver technology features high sensitivity and is capable of maintaining high quality intermodulation immunity and adjacent channel rejection. Even by using multiple IF processes to attain rejection to unwanted and random noise, these processes have to use multiple hardware modules and both analog and digital processing to achieve high quality. The space industry is moving towards higher data rates with improved performance and cost. NASA has been researching the technology to build high rate all-digital receivers for satellite communications. There has been a vast amount of work done both in industry and the government sector to develop components and algorithms to achieve more cost effective solutions. Giant strides have been made by the semiconductor industry in increasing complexity and rapidly improving silicon technology. Improved integration levels and reduced manufacturing costs together with the advantages and flexibility of the latest Digital Signal Processors (DSP) and Direct Digital Synthesizers have now made affordable the development of digital high performance satellite communication systems. These devices together with highly sophisticated design tools have made it possible for researchers and developers to explore large numbers of alternatives and simulate them using digital prototypes.

Applicability of reconfigurable computers in satellite telemetry data processing

The advent of reconfigurable computers (RCs) containing field-programmable gate-array (FPGA) ICs presents a potential solution to the problem of processing telemetry data at the high rates required to support the latest remote-sensing satellites. For example, one satellite scheduled for launch in 1999 by NASAs Earth Science Enterprise project will generate as much Earth-science telemetry in six months as has been collected in NASAs entire 40-year history. NASA is developing software for large, expensive, conventional parallel-processing computer systems in an attempt to meet the expected processing requirements, but whether or not the resulting performance will be adequate remains unknown. For computationally- intensive, repetitive applications like this, RC technology can provide the critical performance edge. The Adaptive Scientific Data Processing (ASDP) project at NASA Goddard Space Flight Center has been investigating RC applications in scientific processing systems. ASDP has developed prototype RC solutions which have achieved processing speeds an order of magnitude faster than a conventional high-end computer workstation alone. This paper presents an overview of remote-sensing satellite telemetry, outlines a particular telemetry processing challenge, describes ASDPs application of RC, discusses the results, and analyzes the current and future state of the art.