Patrick Brooks

Novel approach for a non-etching adhesion promoter for the next generation of IC substrates

Targeted for meeting the requirements of advanced IC manufactures for a non-etching adhesion promoter (NEAP) in the manufacture of sub 10/10 mum line and space, the Securetrade HFz process represents an innovative approach to enhancing the bonding of Ajinomoto buildup film (ABF) materials and comparable films as well as solder masks while not significantly etching the copper conductor to promote adhesion but rather using Silane based chemical adhesion promoters. A complete description of the process and its operating parameters will be presented. As this technical paper will demonstrate, this process achieves superior bonding strength and thermal reliability for not only ABF materials but also high-performance substrates and prepregs in comparison to more traditional copper roughening treatment methods. A complete process characterization has been done to illustrate the merits of Securetrade HFz. The surface was characterized using scanning electron microscopy (SEM), laser interference microscopy (LIM), and atomic force microscopy (AFM) techniques. While the adhesion and thermal performance was done using standard industrial methods such as peel strength.

Multi-layer Copper-Dielectric Adhesion Challenges of 5-12 micron Lines/Spaces for Next Generation SOP (System-on-Package) / Microprocessor Package Substrates

System-on-package (SOP) is a highly integrated systems packaging technology for convergent computing, communication, consumer, and bio-electronic functions in a single package or module. SOP aims to miniaturize systems by the integration of system-level components at microscale in the short term and nanoscale in the future. A key challenge for active and passive component integration is the demand for additional fine pitch wiring in the substrate for interconnecting these thin film embedded components. This adds to the already escalating need for high wiring density substrates driven by transistor density on the IC (Moores Law). This paper addresses a critical process technology for SOP/microprocessor ultra-high density organic build-up substrates, namely, surface treatment of copper and dielectric in multilayer wiring. This process is critical for the challenges of processing and maintaining signal integrity at lines and spaces below 12 mum. A complete description of fine line and space fabrication and a novel copper adhesion process and its operating parameters are presented. We demonstrate this process with superior bonding strength through accelerated reliability testing. Results are shown not only state-of-the-art build-up films but also for high-performance substrates and prepregs in comparison to more traditional copper roughening treatment methods.

EcoFlash™: Next level of enhanced isotropic etchants

With the trend towards miniaturization IC-manufacturers are permanently requested to increase the density of interconnects generating conductors featuring finer lines and spaces. Advanced manufacturing technologies such as Semi-Additive-Processing (SAP) and advanced Modified-Semi-Additive-Processing (aMSAP) were devised, realized and implemented in order to meet the requirements.i According to the roadmaps of the major Original Equipment Manufacturers, line and space requirements of copper conductors become increasingly finer and will be below 5/5μm for the future packaging substrates.iiSAP as well as aMSAP processes are based on pattern plating the desired circuitry on a thin conductive copper seed layer and finalizing the circuit formation afterwards by removal of the respective seed layer using so called flash/differential etching solutions. Herein we report about the performance of the new developed ferric sulfate based EcoFlashTM process for SAP and aMSAP application with the focus on performance and fine line capability in comparison with hydrogen peroxide etchants.

Advanced non-etching adhesion promoter for next generation IC packaging

In this paper findings from the development of a new Non Etching Adhesion Promoter process (NEAP) targeting inner and outer layer bonding are discussed. The herein described approach propagates a nano-scale copper structure that forms a thin anchoring layer with increased surface area, but hardly contributes to the surface roughness. The superb adhesion results obtained to a wide range of dielectrics support the hypothesis of a mechanical type of adhesion mechanism. This paper also outlines detailed examinations on impacts of the adhesion promoter to subsequent processes revealing an unaffected performance generating conductors with excellent geometries for inner- and outerlayer application and clear benefits to the industry.

“Green” PCB production processes

Purpose – The purpose of this paper is to show production process developments and innovations that resolve many of the issues faced with certain process steps for printed circuit board (PCB) manufacturing following “green” practices.Design/methodology/approach – Several key PCB manufacturing processes have been developed or studied with respect to new environmental legislations and practises.Findings – The introduction of new legislations designed to protect the environment require changes to laminate materials, solders, and PCB manufacturing techniques. The effect of new laminate materials on the desmearing and metallising processes have been assessed and recommendations given. The effect of increased thermal stress on plated copper has been assessed. Developments in adhesion enhancement for black oxide alternatives have been made and are presented with their suitability for the newer green laminate materials. The development of a new laminate manufacturing technique to reduce environmental impact is in...