Patrick Hung

Deep submicron microprocessor design issues

Deep-submicron technology allows billions of transistors on a single die, potentially running at gigahertz frequencies. According to Semiconductor Industry Association (SIA) projections, the number of transistors per chip and the local clock frequencies for high-performance microprocessors will continue to grow exponentially in the near future. This ensures that future microprocessors will become ever more complex. However, physical and program behavioral constraints will limit the usefulness of this complexity. Physical constraints include interconnect and device limits, as well as practical limits on power and cost. Program behavioral constraints result from program control and data dependencies, and from unpredictable events during execution. Other challenges include the need for advanced CAD tools to combat the negative effect of greater complexity on design time. Designers will also have to make improvements to preserve computational integrity, reliability, and diagnostic features. Successful implementations will depend on the processor architects ability to foresee technology trends and understand the changing design trade-offs for specific applications, beginning with the differing requirements for client versus server processors. This article discusses these trade-offs in light of industry projections and the many considerations affecting deep submicron technology.

Microprocessor design issues: thoughts on the road ahead

With the scaling of technology promising increases in chip frequency and especially transistor density, system designers must make trade-offs for a rapidly moving target. They must constantly deal with area, time, power, reliability, and technology design trade-offs as well as enormous design complexity at the same time. The driving force in design innovation is the rapid advance in technology. As technology advances and feature size shrinks, the three other design considerations benefit from one process generation to another, resulting in higher speed, smaller area, and reduced power consumption. Here, we look at the technology roadmap and what it means to computer architects, updating our views of six years ago.

Fast division algorithm with a small lookup table

This paper presents a new division algorithm, which requires two multiplication operations and a single lookup in a small table. The division algorithm takes two steps. The table lookup and the first multiplication are processed concurrently in the first step, and the second multiplication is executed in the next step. This divider uses a single multiplier and a lookup table with 2/sup m/(2m+1) bits to produce 2 m-bit results that are guaranteed correct to one ulp. By using a multiplier and a 12.5 KB lookup table, the basic algorithm generates a 24-bit result in two cycles.

Using simple tools to evaluate complex architectural trade-offs

Discusses how students in a processor design class estimated the cost and performance of two chips as part of a case study. This study was based on information available from various public sources. As the chip implementation details had not been released to the public, the instructors assumed the hardware designs were similar to the simulator default configurations. After comparing the performance and the costs, the students used the simulator tools to design improvements to each chip.

CAD Tools for System-Level Modeling and Implementation

Designing a silicon chip is an increasingly complicated process. MICHAEL J FLYNN and PATRICK HUNG discuss the implications. Copyright