Patrick J. Meaney

Reliability, availability, and serviceability (RAS) of the IBM eServer z990

The IBM eServerTM zSeries® Model z990 offers customers significant new opportunity for server growth while preserving and enhancing server availability. The z990 provides vertical growth capability by introducing the concurrent addition of processor/memory books and horizontal growth in channels by the use of extended virtualization technology. In order to continue to support the zSeries legacy for high availability and continuous reliable operation, the z990 delivers significant new features for reliability, availability, and serviceability (RAS). This paper describes these new capabilities, in each case presenting the value of the feature, both in terms of enhancing the self-management capability of the server and its availability.

A 5.2GHz microprocessor chip for the IBM zEnterprise™ system

The microprocessor chip for the IBM zEnterprise 196 (z 196) system is a high-frequency, high-performance design that adds support for out-of-order instruction execution and increases operating frequency by almost 20% compared to the previous 65nm design, while still fitting within the same power envelope. Despite the many difficult engineering hurdles to be overcome, the design team was able to achieve a product frequency of 5.2GHz, providing a significant performance boost for the new system.

IBM zEnterprise redundant array of independent memory subsystem

The IBM zEnterprise® system introduced a new and innovative redundant array of independent memory (RAIM) subsystem design as a standard feature on all zEnterprise servers. It protects the server from single-channel errors such as sudden control, bus, buffer, and massive dynamic RAM (DRAM) failures, thus achieving the highest System z® memory availability. This system also introduced innovations such as DRAM and channel marking, as well as a novel dynamic cyclic redundancy code channel marking. This paper describes this RAIM subsystem and other reliability, availability, and serviceability features, including automatic channel error recovery; data and clock interface lane calibration, recovery, and repair; intermittent lane sparing; and specialty engines for maintenance, periodic calibration, power, and power-on controls.

Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chips ground-breaking RAS features are also described, engineered for maximum reliability and system stability.

RAS design for the IBM eServer z900

The IBM eServer zSeries™ Model 900, or z900, has been designed with major enhancements for hardware reliability, availability, and serviceability (RAS) in support of the zSeries RAS strategy, the eServer self-management technologies, and the z900 design objective of continuous reliable operation. The eServer self-management technologies enable the server to protect itself, to detect and recover from errors, to change and configure itself, and to optimize itself, in the presence of problems and changes, for maximum performance with minimum outside intervention. From the RAS perspective, the longstanding RAS strategy for the IBM S/390® and now the zSeries has provided an excellent foundation for self management. This paper describes the z900 RAS enhancements and how they strengthen the RAS strategy building blocks and provide a basis for autonomic computing.

The zEnterprise 196 System and Microprocessor

The zEnterprise 196 is the latest IBM System zSeries mainframe computer, which builds on IBMs 46-year heritage of compatible enterprise-class machines. This design advances the prior z10 processor pipeline with out-of-order execution to achieve considerable performance gains in legacy online transaction processing and computationally intensive workloads. This article describes the system structure and details of this new high-frequency microprocessor.

The S/390 G5/G6 binodal cache

The IBM S/390® fifth-generation CMOS-based server (more commonly known as the G5) produced a dramatic improvement in system-level performance in comparison with its predecessor, the G4. Much of this improvement can be attributed to an innovative approach to the cache and memory hierarchy: the binodal cache architecture. This design features shared caching and very high sustainable bandwidths at all points in the system. It contains several innovations in managing shared data, in maintaining high bandwidths at critical points in the system, and in sustaining high performance with unparalleled fault tolerance and recovery capabilities. This paper addresses several of these key features as they are implemented in the S/390 G5 server and its successor, the S/390 G6 server.

A new class of array codes for memory storage

In this article we describe a class of error control codes called “diff-MDS” codes that are custom designed for highly resilient computer memory storage. The error scenarios of concern range from simple single bit errors, to memory chip failures and catastrophic memory module failures. Our approach to building codes for this setting relies on the concept of expurgating a parity code that is easy to decode for memory module failures so that a few additional small errors can be handled as well, thus preserving most of the decoding complexity advantages of the original code while extending its original intent. The manner in which we expurgate is carefully crafted so that the strength of the resulting code is comparable to that of a Reed-Solomon code when used for this particular setting. An instance of this class of algorithms has been incorporated in IBMs zEnterprise mainframe offering, setting a new industry standard for memory resiliency.

Storage hierarchy to support a 600 MHz G5 S/390 microprocessor

Although a microprocessors maximum frequency and internal design are important, the storage hierarchy is the primary reason for the large system performance improvement of the S/390 G5 compared to the G4. The improvement is achieved with an L2 cache, system controller and memory interface clocked at 1/4 the microprocessor frequency.

The IBM z13 memory subsystem for big data

The IBM z13™ system uses the new IBM Centaur memory buffer chip, along with system topology changes, to more than triple system memory capacity (relative to the IBM zEnterprise™ EC12) to 10 TB, and more than triple the drawer-level memory bandwidth to 384 GB/s, and double the DIMM (dual in-line memory module) frequency to 1,600 MHz. The z13 eliminates an asynchronous interface for better store protect key performance. The new memory power save feature on the z13 extends the benefit of the IBM customer power save mode and the IBM cycle steering recovery for lower power. The z13 system builds upon the IBM redundant array of independent memory (RAIM), introduced on the IBM z196 system. New reliability features include single-channel memory bus replay, incremental background lane calibration, and memory scrub hard-error management. An innovative fetch and store tagging architecture, along with a memory quiesce engine, is added to detect RAIM asynchronization events and to re-synchronize memory channels for better performance.