Patrick Lysaght

Invited Paper: Enhanced Architectures, Design Methodologies and CAD Tools for Dynamic Reconfiguration of Xilinx FPGAs

The paper describes architectural enhancements to Xilinx FPGAs that provide better support for the creation of dynamically reconfigurable designs. These are augmented by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from Xilinxs commercial CAD tools

A Lightweight Approach for Embedded Reconfiguration of FPGAs

This paper presents a lightweight approach for embedded reconfiguration of Xilinx Virtex II/spl trade/ series FPGAs. A hardware and software infrastructure is reported that enables an FPGA to dynamically reconfigure itself under the control of a soft microprocessor core that is instantiated on the same array. The system provides a highly integrated, lightweight approach to dynamic reconfiguration for embedded systems. It combines the benefits of intelligent control, fast reconfiguration and small overhead.

A Virtual File System for Dynamically Reconfigurable FPGAs

Platform FPGAs have dramatically changed the role of FPGAs in embedded systems. With increased density and immersed complex IPs, FPGAs no longer simply play ‘a role’ in embedded systems – FPGAs are embedded systems. To accommodate the increased system capability of Platform FPGAs, they also host a rich embedded software environment. Embedded Linux has emerged as a common software infrastructure for embedded systems in general and is also being employed in FPGA-based embedded systems.

Of gates and wires

Summary form only given. Research into interconnection networks pre-dates the development of integrated circuits and even the transistor. As a result, much pioneering and fundamental research has established an enormous body of knowledge in this field. Recently, we have turned our attention to the design of crossbar switches using dynamically reconfigurable FPGAs. Our first effort resulted in a reconfigurable crossbar structure that introduced novel circuit techniques and set new performance benchmarks. More recently, we have exploited the availability of FPGAs with integrated microprocessors and dynamic reconfiguration to design multistage networks based on strictly, nonblocking Clos architectures. The results are very encouraging and improve the benchmarks achieved with our original design for all but one metric. Since interconnection is fundamental to all processing architectures we hope that our work find relevance in future reconfigurable architectures.

FPGAs as meta-platforms for embedded systems

Platform-based design is one of the key strategies that is promoted for successfully coping with the most complex, system-on-chip designs. Its basic premise is that the levels of design productivity needed to counter the intrinsic complexity of such embedded systems will only be achieved by extensive, planned design re-use. The platform concept originated with ASICs but evolved rapidly to FPGAs. In this paper, we investigate the phenomenon of FPGA platforms using the Xilinx Virtex/spl trade/-II Pro series of Platform FPGAs as our reference model. We identify and categorize their principal characteristics and seek to differentiate them from their ASIC predecessors. We make the case for regarding Platform FPGAs as meta-platforms because of the extent to which they extend the original concept of platform-based design. Looking forward, we offer some conjectures as to the nature of future FPGA platforms and some of the challenges that researchers will face.

Future design tools for platform FPGAs

According to current projections, programmable platforms will dominate ASIC design starts as the semiconductor industry moves to 90 nm process technology and beyond. In this paper, we assess the implications of this trend and explore the impact it will have on system-level design methodologies for FPGAs. We review current research and practice in system-level design and attempt to assess how much of the ASIC experience will be relevant to future FPGA designers.

Significant papers from the first 25 years of the FPL conference

The list of significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented in this paper. These 27 papers represent those which have most strongly influenced theory and practice in the field.

The First 25 Years of the FPL Conference: Significant Papers

A summary of contributions made by significant papers from the first 25 years of the Field-Programmable Logic and Applications conference (FPL) is presented. The 27 papers chosen represent those which have most strongly influenced theory and practice in the field.

RAW 2016 Keynotes

This presentation makes the case for adding shared-memory reconfigurable logic into standard multi-purpose dynamically allocated cloud infrastructure. We look at the opportunities for offloading network, storage, and compute related functions from the CPU to the reconfigurable logic. Next we discuss how reconfigurable logic can be used in Big Data infrastructure, and we present an end-to-end example that brings cloud, big data, and reconfigurable computing together. About the Speaker: H. Peter Hofstee (Ph.D. California Inst. of Technology, 1995) is a distinguished research staff member at the IBM Austin Research Laboratory, USA, and a part-time professor in Big Data Systems at Delft University of Technology, Netherlands. Peter is best known for his contributions to heterogeneous computer architecture as the chief architect of the Synergistic Processor Elements in the Cell Broadband Engine processor, used in the Sony Playstation3 and the first supercomputer to reach sustained Petaflop operation. After returning to IBM research in 2011 he has focused on optimizing the system roadmap for big data, analytics, and cloud, including the use of accelerated compute. His early research work on coherently attached reconfigurable acceleration on Power 7 paved the way for the new coherent attach processor interface on POWER 8. Peter is an IBM master inventor with more than 100 issued patents and a member of the IBM Academy of technology. Enabling Software Engineers to Program Heterogeneous, Reconfigurable SoCs Patrick Lysaght – Xilinx, San Jose, CA, USA Abstract: This talk describes a new, open-source framework for designing with Xilinx Zynq devices, a class of All Programmable Systems on Chip (APSoCs) which integrates multiple processors and Field Programmable Gate Arrays (FPGAs) into single integrated circuits. The main goal of framework is to make it easier for designers of embedded systems to exploit the unique benefits of APSoCs in their applications. Specifically, it enables the architects, engineers and programmers who design embedded systems to exploit the capabilities of Zynq APSoCs without having to use ASIC-style, CAD tools to design programmable logic circuits. Instead the APSoC is programmed in Python and the code is developed and tested directly on the embedded system. The programmable logic circuits are imported as hardware libraries and programmed through their APIs, in essentially the same way that software libraries are imported and programmed. This talk describes a new, open-source framework for designing with Xilinx Zynq devices, a class of All Programmable Systems on Chip (APSoCs) which integrates multiple processors and Field Programmable Gate Arrays (FPGAs) into single integrated circuits. The main goal of framework is to make it easier for designers of embedded systems to exploit the unique benefits of APSoCs in their applications. Specifically, it enables the architects, engineers and programmers who design embedded systems to exploit the capabilities of Zynq APSoCs without having to use ASIC-style, CAD tools to design programmable logic circuits. Instead the APSoC is programmed in Python and the code is developed and tested directly on the embedded system. The programmable logic circuits are imported as hardware libraries and programmed through their APIs, in essentially the same way that software libraries are imported and programmed. The framework combines four main elements: the use of a high-level productivity language, Python in this case Python-callable hardware libraries based on FPGA overlays a web-based architecture incorporating the open-source Jupyter Notebook infrastructure served from Zynqs embedded processors Jupyter Notebooks client-side, web apps The result is a programming environment that is web-centric so it can be accessed from any browser on any computing platform or operating system. It enables software programmers to work at higher levels of design abstraction and to re-use both software and hardware libraries. The framework is inherently extensible and integrates coherently with hardware–dependent code written in C and C++. The talk concludes with a live demonstration, an outline of areas for continued development, and a call for community participation. About the Speaker: Patrick Lysaght is a Senior Director in Xilinx Research Labs, San Jose, California. He leads a group whose research interests include system-level performance analysis, modeling, and design for heterogeneous, reconfigurable architectures. He is especially interested in emerging design methodologies based on open source technologies. Patrick also directs the worldwide operation of the Xilinx University Program (XUP). Before joining Xilinx, he held positions as a senior lecturer at the University of Strathclyde (Glasgow) and at the Institute for System Level Integration (Livingston, Scotland). He started his career in research and development with Hewlett Packard (Edinburgh) before going on to hold a number of technical and marketing positions. Patrick has co-authored more than fifty technical papers, co-edited two books on programmable logic and holds ten US patents. He has served on the technical committees of numerous international conferences and is chairman of the steering committee for FPL, the world’s largest conference dedicated to field programmable logic. Two of his papers on dynamically reconfigurable logic feature among the most significant research papers of the first 25 years of FPL. Patrick holds a BSc (Electronic Systems) from the University of Limerick, Ireland and an MSc degree (Digital Techniques) from Heriot-Watt University in Edinburgh, Scotland. 2016 IEEE International Parallel and Distributed Processing Symposium Workshops /16

Guest Editorial Special Section on Embedded Reconfigurable Computing Systems

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