Paul Anthony Moore

A highly digitized multimode receiver architecture for 3G mobiles

A highly digitized multimode receiver architecture is described. It is configured primarily for the Universal Mobile Telecommunication System (UMTS) and Global System for Mobile Communications (GSM) modes, but has the potential to operate in other modes such as cdma2000 as well. The receiver uses a single down conversion to mix the RF signal to a zero intermediate frequency (IF) for UMTS mode and a low IF for GSM. It uses a reconfigurable analog-to-digital converter (ADC) to digitize the IF signals as early as possible and to transfer most of the channel filtering into the digital domain. Only a minimum of automatic gain control (AGC) is employed. The architecture aims to maximize reuse of common hardware and to make significant gains in terms of design costs, size, and adaptability. System simulations confirm the feasibility and performance of the new concept.

A low-IF polyphase receiver for GSM using log-domain signal processing

The design of a polyphase receiver for GSM is presented. Compared with a superhet solution, it offers similar performance but is very much easier to integrate on silicon without the need for off-chip channel filters. Compared with a zero-IF solution, a substantial improvement in performance is achieved by virtue of eliminating the problems with DC offsets and IP/sub 2/ generation. The use of log-domain signal processing leads to simplifications in the digital baseband and eliminates the need for AGC.

A re-configurable receiver architecture for 3G mobiles

A re-configurable, highly-integrated receiver architecture is described for use in 3/sup rd/-generation mobile handsets. It is intended for dual-mode UMTS and GSM operation but should be capable of operating in other modes such as CDMA2000. The receiver achieves its adaptability by using a single down-conversion approach to either a zero IF or a near-zero IF and then digitizing as much of the IF signal chain as possible. Notwithstanding its reconfigurability, system simulations indicate that the receiver should achieve state-of-the-art performance.

A low-IF, polyphase receiver for DECT [in BiCMOS]

The design of a single-chip, polyphase receiver for DECT (Digital Enhanced Cordless Telecommunications) is presented offering state-of-the-art sensitivity and selectivity. Compared with an alternative zero-IF (intermediate frequency) solution for DECT, very substantial improvements in performance are achieved with a chip of modest area.