Paul Arthur Layman

Development of robust interconnect model based on design of experiments and multiobjective optimization

When designing an integrated circuit, it is important to take into consideration random variations arising from process variability. Traditional optimization studies on VLSI interconnect attempt to find the deterministic optimum of a cost function but do not take into account the effect of these random variations on the objective. We have developed an effective methodology based on TCAD simulation and design of experiments to optimize interconnect including the effects of process variations. The aim of the study is to search for optimum designs that both meet the performance specification and are robust with respect to process variations. A multiobjective optimization technique known as Normal Boundary Intersection is used to find evenly-spaced tradeoff points on the Pareto curve. Designers can then select designs from the curve without using arbitrary weighting parameters. The proposed methodology was applied to a 0.12 /spl mu/m CMOS technology; optimization results are discussed and verified using Monte Carlo simulation.

Statistical modeling of MOS devices for parametric yield prediction

Abstract In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations.

Worst-case analysis and statistical simulation of MOSFET devices based on parametric test data

Abstract A practical and efficient approach for estimating the MOSFET device and circuit performance distributions is presented. The proposed method is based on the Latin hypercube sampling technique and direct extracting and utilizing the statistical information obtained from a population of parametric test data. Using this approach, a set of worst-case models taking into account data correlations and equal probability constraints is developed. The procedure allows for a systematical and accurate way to predict the performance spread and worst case of MOSFET circuits, as well as a greatly reduced computation time for statistical simulation. Measured data of two digital circuits are included in support of the modeling work.