Paul D. Dresselhaus

1 V and 10 V SNS Programmable Voltage Standards for 70 GHz

Programmable Josephson voltage standards (PJVSs) in combination with fast switchable DC current sources have opened up new applications in the field of low-frequency AC metrology. The growing interest in output voltages of up to plusmn10 V initiated efforts by several National Metrological Institutes to realize 10 V PJVSs. Presently, only 10 V PJVSs from PTB based on SINIS junctions have been successfully incorporated into existing setups for AC metrology. However, the fabrication of 10 V SINIS arrays that are driven at 70 GHz suffers from very low yield. The recent technological progress made at NIST enabled the drop-in replacement of the low-yield SINIS arrays by more robust SNS arrays. The N-material is an amorphous NbxSi1-x alloy near the metal-insulator transition and is deposited by co-sputtering. For the first time, fully operational 1 V and 10 V PJVSs with SNS junctions that are suitable for a 70 GHz drive have been fabricated and tested. This work was done in close cooperation between NIST and PTB.

Precision Differential Sampling Measurements of Low-Frequency Synthesized Sine Waves With an AC Programmable Josephson Voltage Standard

We have developed a precision technique to measure sine-wave sources with the use of a quantum-accurate AC programmable Josephson voltage standard. This paper describes a differential method that uses an integrating sampling voltmeter to precisely determine the amplitude and phase of high-purity and low-frequency (a few hundred hertz or less) sine-wave voltages. We have performed a variety of measurements to evaluate this differential technique. After averaging, the uncertainty obtained in the determination of the amplitude of a 1.2 V sine wave at 50 Hz is 0.3 muV/V (type A). Finally, we propose a dual-waveform approach for measuring two precision sine waves with the use of a single Josephson system. Currently, the National Institute of Standards and Technology (NIST) is developing a new calibration system for electrical power measurements based on this technique.

Hybrid superconducting-magnetic memory device using competing order parameters

In a hybrid superconducting-magnetic device, two order parameters compete, with one type of order suppressing the other. Recent interest in ultra-low-power, high-density cryogenic memories has spurred new efforts to simultaneously exploit superconducting and magnetic properties so as to create novel switching elements having these two competing orders. Here we describe a reconfigurable two-layer magnetic spin valve integrated within a Josephson junction. Our measurements separate the suppression in the superconducting coupling due to the exchange field in the magnetic layers, which causes depairing of the supercurrent, from the suppression due to the stray magnetic field. The exchange field suppression of the superconducting order parameter is a tunable and switchable behaviour that is also scalable to nanometer device dimensions. These devices demonstrate non-volatile, size-independent switching of Josephson coupling, in magnitude as well as phase, and they may enable practical nanoscale superconducting memory devices.

10V programmable Josephson voltage standard circuits using NbN∕TiNx∕NbN∕TiNx∕NbN double-junction stacks

Using NbN∕TiNx∕NbN∕TiNx∕NbN double-junction stack technology we have demonstrated a programmable Josephson voltage standard chip that operates up to 10.16V output voltage cooled with a two-stage Gifford–McMahon cryocooler. The circuit uses double-junction stacks, where two junctions are fabricated in each stack, in order to integrate 327 680 junctions into a 15.3mm×15.3mm chip. A 1-to-32 microwave distribution circuit is also integrated on the chip. The chip is divided into 22 cells, which perform as an 11-bit digital-to-analog converter. The 21 working cells include 307 200 junctions biased with 16GHz microwaves at 10.2K that generated flat voltage steps with current margins greater than 1mA, which indicates good uniformity of the stacked junctions.

AC coupling technique for Josephson waveform synthesis

We demonstrate a new bias technique that uses low-pass and high-pass filters to separate the current paths of the sampling and signal frequencies in a Josephson waveform synthesizer. This technique enables the output voltage of the array to be directly grounded by removing the low-frequency common mode signal that previously prevented direct measurement of the array voltage with low-impedance instruments. We directly measure the harmonic spectra of 1 kHz and 50 kHz synthesized sine waves. We also use a thermal transfer standard to compare the rms voltages of synthesized sine waves at frequencies from 1 kHz to 50 kHz. Finally, we describe a new circuit that should enable a significant increase in output voltage by allowing several distributed arrays to be biased in parallel at high frequency, while combining their low frequency output voltages in series.

Systematic error analysis of stepwise approximated AC waveforms generated by a Programmable Josephson Voltage Standard

We have measured stepwise-approximated sine waves generated by a programmable Josephson voltage standard (PJVS) with several different output configurations. These data are analyzed to characterize the dominant error mechanisms for RMS applications, such as AC-DC difference measurements of thermal voltage converters (TVCs). We present detailed explanations of the fundamental causes and consequences of systematic errors that arise from transitions and consider the overall uncertainties for PJVS ac metrology using this synthesis method. We show that timing-related errors are sufficient to make this waveform synthesis approach impractical for RMS audio-frequency applications. The implications of providing the load current required by devices of low input impedance, such as TVCs, are also discussed.

Error and Transient Analysis of Stepwise-Approximated Sine Waves Generated by Programmable Josephson Voltage Standards

We are developing a quantum-based 60 Hz power standard that exploits the precision sinusoidal reference voltages synthesized by a programmable Josephson voltage standard (PJVS). PJVS systems use series arrays of Josephson junctions as a multibit digital-to-analog converter to produce accurate quantum-based dc voltages. Using stepwise-approximation synthesis, the system can also generate arbitrary ac waveforms [i.e., an ac programmable Josephson voltage standard (ACPJVS)] and, in this application, produces sine waves with calculable root mean square (rms) voltage and spectral content. The primary drawback to this ACPJVS synthesis technique is the uncertainty that results from switching between the discrete voltages due to finite rise times and transient signals. In this paper, we present measurements and simulations that elucidate some of the error sources that are intrinsic to the ACPJVS when used for rms measurements. In particular, we consider sine waves synthesized at frequencies up to the audio range, where the effect of these errors is more easily measured because the fixed transition time becomes a greater fraction of the time in each quantized voltage state. Our goal for the power standard is to reduce all error sources and uncertainty contributions from the PJVS-synthesized waveforms at 60 Hz to a few parts in 107 so that the overall uncertainty in an ac power standard will be a few parts in 106.

Practical high-resolution programmable Josephson Voltage standards using double- and triple-stacked MoSi/sub 2/-barrier junctions

We have developed vertically stacked superconductor normal-metal-superconductor Josephson junction technology for the next-generation quantum voltage standards. Stacked junctions provide a practical way of increasing the output voltage and operating margins. In this paper, we present fully functioning programmable voltage standard chips with double- and triple- stacked MoSi/sub 2/ barrier Josephson junctions with over 100 000 junctions operating simultaneously on a 1 cm /spl times/ 1 cm chip. The maximum output voltages of the double- and triple-stacked chips were 2.6 V and 3.9 V, with respective operating current margins of 2 mA and 1 mA. A new trinary-logic design is used to achieve higher voltage resolution. Thermal transport in these high-density chips will be briefly discussed.

Co-Sputtered Amorphous Nb

Co-sputtered amorphous NbxSi1-x has been developed as a barrier material for Josephson-junction array circuits. This material is quite promising as a normal-metal barrier for state-of-the-art Josephson voltage standards. In addition, the capability of tuning the barrier resistivity over a wide range that includes the metal-insulator transition could lead to applications in high-speed superconductive electronics. The electrical characteristics and uniformity of amorphous NbxSi1-x-barrier junctions are similar to those of other normal-metal barriers, but the superior etching properties makes this barrier material especially promising for tall, stacked junctions that are required for high-junction-density applications. Under appropriate deposition conditions, the reproducibility of devices with co-sputtered amorphous NbxSi1-x is sufficient to produce high-quality stacked-junction superconductive devices

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The Boltzmann constant k was measured by comparing the Johnson noise of a resistor at the triple point of water with a quantum-based voltage reference signal generated with a superconducting Josephson-junction waveform synthesizer. The measured value of k = 1.380 651(17) × 10−23 J K−1 is consistent with the current CODATA value and the combined uncertainties. This is our first measurement of k with this electronic technique, and the first noise-thermometry measurement to achieve a relative combined uncertainty of 12 parts in 106. We describe the most recent improvements to our Johnson-noise thermometer that enabled the statistical uncertainty contribution to be reduced to seven parts in 106, as well as the further reduction of spurious systematic errors and electromagnetic interference effects. The uncertainty budget for this measurement is discussed in detail.