Paul E. Riley

Comparison of etch rates of silicon nitride, silicon dioxide, and polycrystalline silicon upon O2 dilution of CF4 plasmas

The etch rates of Si3N4, SiO2, and doped polycrystalline silicon with CF4 plasmas have been examined as a function of O2 dilution and radio frequency (rf) (13.56 MHz) power density at constant residence time (25 mTorr and 25 sccm total process gas flow rate) at 22±2 °C in a batch reactor. At fixed reactor pressure and process gas composition, the etch rates of these materials increase linearly, with different slopes, with increasing rf power density. Under the conditions studied, the etch rates of SiO2 are lower than those of the other two materials and are primarily a function of rf power for CF4 plasmas that are diluted with 0%–25% O2 by flow rate. In comparison, the etch rates of Si3N4 and doped polycrystalline silicon are functions of both rf power density and gas composition, although at each rf power level (200, 300, and 400 W) the Si3N4 etch rate reaches a plateau at an O2 dilution of ∼10%–15% by flow rate. Although the doped polycrystalline silicon etch rate exhibits similar behavior at 200 and 30...

Plasma Etching of Aluminum Metallizations for Ultralarge Scale Integrated Circuits

The metallizations which interconnect devices formed on silicon wafers have evolved from a single level of «broad» lines of aluminum to very narrow lines (<1 μm in width), often more than two levels per chip. Whereas broad lines may be satisfactorily defined by solution or «wet» etching, narrow lines must be defined by plasma etching to maintain dimensional and profile control. Moreover, simple aluminum metallization has become complex, generally consisting of a composite of barrier and antireflecting layers which sandwich the aluminum film. In addition, the aluminum film itself is probably «doped» with silicon and copper for solid solubility and electromigration considerations. Consequently, plasma etching of «aluminum» has become more complicated in the last few years

Composite metal etching for submicron integrated circuits

To define metal lines for composite metal structures for integrated circuits with small pitches ( 0.1 /spl mu/m/line, respectively, without leaving metallic residue and without undercutting the masking layer. These goals have been achieved for a layered metal structure of Ti-W/Al-Cu(2%)/Ti-W with an Applied Materials AME 8330 batch system after examining process parameter spaces defined by the following: (i) reactor pressure, (ii) dc bias voltage, and (iii) gas composition for these two films. The selectivity between Al-Cu(2%) and photoresist increases with decreasing dc bias voltage and increasing Cl/sub 2/ content of Cl/sub 2//BCl/sub 3//CHF/sub 3/ gas mixtures. In comparison, the selectivity between Ti-W and photoresist increases only with increasing CF/sub 4/ content of CF/sub 4//Cl/sub 2/ gas mixtures; changes in the other variables examined in this work with Ti-W have no significant effect on selectivity. >

Implementation of tungsten metallization in multilevel interconnection technologies

The techniques of experimental design and response-surface methodology have been used to produce empirical models of the deposition and etchback of tungsten in commercially available reactors for a tungsten plug technology. Deposition was carried out in a Genus 8402 LPCVD (low-pressure chemical vapor deposition) batch reactor by the H/sub 2/ reduction of WF/sub 6/. Response-surfaces for deposition rate, sheet resistance uniformity, resistivity, and film stress were developed as a function of reactor pressure, reactor temperature, and flow rate of WF/sub 6/ at a fixed H/sub 2/ flow rate using linear-interactive models. A thin layer of TiN was used to ensure adhesion of tungsten to SiO/sub 2/. Etchback of the composite layer of W/TiN to form via plugs was performed in a Tegal 804 single-wafer system with a two-step process using mixtures of SF/sub 6/ with C/sub 2/F/sub 6/ and He with Cl/sub 2/ in step 1 and step 2, respectively. Process parameters for both steps were obtained from quadratic models of etch rate and etch uniformity. >

Advanced 'contact engineering' for submicron VLSI multilevel metallization

Two contact engineering methods developed for submicron contact openings are described. The two methods, SCOPE (simultaneous contact and planarization etch) and PACE (planarization after contact etch), interchange the process sequences of dielectric planarization and contact etch to achieve uniform contact etch. Both etching processes eliminate the need for oxide reflow thereby minimizing the thermal budget after source/drain formation. Since the dielectric is planarized either during the contact etch (e.g., with SCOPE) or after contact etch (e.g., with PACE), the need for extensive overetching of the oxide due to the dissimilar contact depths is also eliminated. As a result, contact resistance and leakage currents are significantly reduced in comparison to results obtained with dielectrics planarized before etching. In addition, etching of field oxide due to pattern misalignment is minimized since the contacts are of similar depth. >

Etch Selectivity Between Phosphorus‐Doped SiO2 and TiSi2

The etch rates of phosphorus-doped SiO 2 (PSG) and TiSi 2 , which is used on source/drain, and polycrystalline silicon contacts of metal oxide semiconductor devices have been measured in an O 2 /CHF 3 plasma for a process designed to produce contact openings with sloped sidewalls that concomitantly achieves adequate etch selectivity between PSG and underlying TiSi 2 (∼10:1). Although the PSG etch rate is visually unaffected by the addition of 5 to 33% O 2 by flow rate to this CHF 3 plasma, the TiSi 2 etch rate increases linearly with increasing O 2 content in the plasma

Formation of Contacts in a Planarized SiO2 / Si3 N 4 / SiO2 Dielectric Structure

The formation of vertical contact openings through planarized dielectric layers requires either very high etch selectivity between SiO 2 and silicon substrates or modification of the dielectric film structure to offset the need for extreme etch selectivity

Trilayer Photoresist Definition with High Pressure Plasmas

Pattern transfer from a mask plate to a photoresist film by multilayer resist techniques consists of image transfer to a thin photosensitive layer which is separated from a thick underlying organic planarizing layer by an inorganic barrier film. After exposure and development of the imaging photoresist pattern transfer is completed by successively etching the intermediate and planarizing coatings such that the vertical profiles which are defined in the imaging layer are transferred into the lower layers. Reported herein is a two-step etching process which is carried out at high pressure (>1000 mtorr) and low radio frequency (RF) (0.4 mHz) for both steps in a Perkin-Elmer Omni-Etch 10000 single-wafer system.

Reactor characterization for a process to etch Si/sub 3/N/sub 4/ formed on thin SiO/sub 2/

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si/sub 3/N/sub 4/ which has been formed on thin thermally grown SiO/sub 2/ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss ( approximately 0.08 mu m), vertical profiles after etch, retention of some of the underlying thermal SiO/sub 2/, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O/sub 2/ concentration by flow rate (30 to 70%) of an O/sub 2//CHF/sub 2/ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure ( approximately 25 mTorr), 50-60% O/sub 2/ by flow rate in O/sub 2//CHF/sub 3/, and low DC bias (-200 to -250 V). >

Reactor Characterization for an SiO2 Plasma Etchback Process with Response‐Surface Methodology: Effects of Interelectrode Spacing

The characteristic of CF 4 /O 2 plasmas which are used to etch composite layers of sacrificial photoresist and underlying SiO 2 have been examined with experimental design and modeled empirically by response-surface methodology using a Lam Research Autoetch 480 single-wafer system. The effects of variations of process gas flow rates for CF 4 (150-200 sccm) and O 2 (0-50 sccm), reactor pressure (900-2000 mtorr), and interelectrode spacing (4-6 mm) on the etch rates of SiO 2 and photoresist were explored at fixed radio frequency power (500 W at 13.56 MHz) at 22° ± 2°C. Process optimization using the empirical models to attain suitable etch rates for both films for planarization of a composite layer of photoresist and SiO 2 with high etch uniformity was achieved at 500 W of RF power, 1450 mtorr, 150 sccm of CF 4 , 0 sccm O 2 , and a spacing of 5.5 mm. Hence, for a CF 4 plasma with this reactor adequate planarization is obtained without the use of O 2 . The addition of small concentrations of O 2 to a CF 4 plasma resulted in increasingly higher etch rates for photoresist as the process progressed