Paul H. Gailus

On-die parasitic effects and their impact on high-speed bipolar IC design

On-die parasitics can impose a significant barrier in the push to achieve higher speeds and integrate more functions. The various parasitics of devices and interconnects and their impact on circuit performance are reviewed. Within a given technology, there are a number of steps that can be taken to minimize the effects of parasitics and thereby maximize fast signal performance. These steps involve the approximate layout and sizing of individual devices, as well as floorplanning and routing of the functional blocks. Circuit design also plays a critical role in this context. The selection of circuit topology, physical partitioning, component values, and operating bias and signal levels has a large impact on high frequency performance. The author highlights some of these important considerations in high-speed IC design and layout.<<ETX>>

Quadrature generation and phase adjustment architecture for Cartesian loop transmitter

Linearization is used in cellular radio portable transmitters to improve transmitted signal Adjacent Channel Coupled Power Ratio ( ACCPR) while keeping high RF power amplifier (RFPA) efficiency. Cartesian feedback loop based linearizer are commonly used in linear digital cellular portable transmitters ( TETRA, iDENtrade, etc. ). Cartesian feedback linearizers enable improved adjacent and alternative channels ACP while still allowing the RFPA to operate close to its saturation point, which maintains good RFPA efficiency. Phase training is used in a Cartesian feedback loop to correctly adjust loop phase to facilitate negative feedback (stability). This paper discuss architectures for quadrature generation and phase adjustments in Cartesian loop transmitters.