Paul Henri Marie Cautereels

Novel data storage for H.264 motion compensation: system architecture and hardware implementation

Quarter-pel (q-pel) motion compensation (MC) is one of the features of H.264/AVC that aids in attaining a much better compression factor than what was possible in preceding standards. The better performance however also brings higher requirements for computational complexity and memory access. This article describes a novel data storage and the associated addressing scheme, together with the system architecture and FPGA implementation of H.264 q-pel MC. The proposed architecture is not only suitable for any H.264 standard block size, but also for streams with different image sizes and frame rates. The hardware implementation of a stand alone H.264 q-pel MC on FPGA has shown speeds between 95.9 fps for HD1080p frames, 229 fps for HD 720p and between 2502 and 12623 fps for CIF and QCIF formats.

Fast H.264 intra prediction for network video processing

This letter proposes a fast parallel and deeply pipelined architecture for realtime H. 264 intra 4x4 prediction capable of handling up to 32 High Definition video streams (1920x1080 @ 30 fps) simultaneously, while offering high flexibility and consuming only a fraction of resources available on modern FPGAs. The design has been validated on target using a state of the art Altera Stratix IV FPGA.