Paul Lowy

Timing driven placement using complete path delays

The Timing Drive Placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during placement. TDP is significant because convergence to a timed wirable solution early in the physical design cycle is achieved, or else it becomes apparent that logic changes are required.

Design automation and the programmable logic array macro

The Programmable Logic Array (PLA) macro is a physical structure which simplifies LSI chip design while yielding high density and good performance. In addition, the inherent order and regularity of this structure provide opportunities to speed design through automated logic documentation, design verification by computer simulation, and computer-automated physical design. In this paper a chip design methodology is described which is based on the use of PLA structures (or macros) within a chip. Logic functions in array form are specified in a compact notation that is automatically converted either to array personalization patterns or to conventional logic blocks for input to existing checking and testing software. Simulation of any logic array is performed by a single program subroutine operating on these patterns. In addition, the simple, regular nature of the logic array lends itself to automatic generation of the layout geometries necessary to actually build the array on a silicon chip. Programs developed for these purposes and the PLA macro design procedures are described in the context of an engineering design system.