Paul R. Besser

Texture analysis of damascene-fabricated Cu lines by x-ray diffraction and electron backscatter diffraction and its impact on electromigration performance

The texture of electroplated Cu lines of 0.375, 0.5 and 1.5 μm widths with Ta and TiN barrier layers was analyzed using x-ray pole figure and electron backscatter diffraction (EBSD) techniques. Both techniques indicate a strong (111) fiber texture relative to the bottom surface of the trench for samples with a Ta barrier layer and a 400 °C, 30 min, postelectroplating anneal. Samples with a TiN barrier and no anneal exhibit a weak (111) texture. For both barrier layers the quality of the texture, as measured by (111) peak intensity, fraction of randomly oriented grains and (111) peak width, degrades with decreasing linewidth. EBSD data also indicate (111) texture relative to the sidewalls of the trench in samples with a Ta barrier and postelectroplating anneal. Electromigration tests at 300 °C of 0.36 μm damascene Cu lines with the same process conditions show that samples with very weak (111) texture have median time to failures that exceed those of the strongly textured Cu lines. These results indicate t...

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.

Self-aligned CoSi/sub 2/ for 0.18 /spl mu/m and below

CoSi/sub 2/ is being used commonly for the advanced IC technologies. There are several process choices to be made for the formation of a high yielding and reproducible silicide. In this paper the various CoSi/sub 2/ technologies are discussed. The scalability of the process of record, the Co/Ti(cap) process are presented for 0.18 /spl mu/m and below.

Band offset induced threshold variation in strained-Si nMOSFETs

Due to the offset in the valence band, strained-Si nMOSFETs exhibit a -100 mV threshold shift and 4% degradation of the subthreshold slope per each 10% increase of Ge content in the relaxed SiGe layer. The correlation between the threshold shift and strained layer thickness is investigated based on device simulations. In a certain range of the strained-Si layer thickness, the threshold and subthreshold slope change gradually, posing a concern of larger device parameter variation. A larger threshold distribution is observed in devices fabricated with a strained layer thickness comparable to the depletion depth.

Analysis of grain-boundary structure in Al–Cu interconnects

The role of crystallographic texture in electromigration resistance of interconnect lines is well documented. The presence of a strong (111) fiber texture results in a more reliable interconnect structure. It is also generally accepted that grain-boundary diffusion is the primary mechanism by which electromigration failures occur. It has been difficult to this point, however, to obtain statistically reliable information of grain-boundary structure in these materials as transmission electron microscopy investigations are limited by tedious specimen preparation and small, nonrepresentative, imaging regions. The present work focuses upon characterization of texture and grain-boundary structure of interconnect lines using orientation imaging microscopy, and particularly, upon the linewidth dependence of these measures. Conventionally processed Al–1%Cu lines were investigated to determine the affects of a postpatterning anneal on boundary structure as a function of linewidth. It was observed that texture tende...

Comparative study of Ni-silicide and Co-silicide for sub 0.25-mm technologies

In this work, the phase formation is compared for Ni- and Co-silicidation with and without Ti cap. In addition, the electrical performance of Ni-silicidation with and without Ti-cap is investigated and compared to the performance of a Co-silicidation process with a Ti cap that has the same Si consumption. The lateral confinement of the silicide in the active areas is also studied.

Simulation and experiments of stress migration for Cu/low-k BEoL

Stress migration (SM) or stress-induced voiding experiments were conducted for two back-end-of-line (BEoL) technologies: Cu/FTEOS and Cu/low-k. Experiments have shown the mean time to failure (MTF) depends on inter-layer dielectric (ILD) materials properties, ILD stack and metal line width. Stress migration is worse in Cu/low-k, manifesting as significantly reduced MTF under accelerated testing. Line width also has a more profound effect on stress migration reliability in Cu/low-k than in Cu/FTEOS. Wider lines produce higher failure rates, due to larger stress magnitudes in Cu and larger active diffusion volumes. Stress modeling using finite element analysis (FEA) was performed to quantify the stress fields in the via-chain test structure used for SM reliability testing. In order to account for the effect of process steps on stress evolution, a process-oriented modeling approach was developed. Stress in the metal line is a function of ILD properties, ILD stack and metal line width. The concept of an SM risk index is proposed to assess BEoL stress migration reliability from both stress and energy perspectives. Comparison of the SM risk index for Cu/FTEOS and Cu/low-k shows that the latter is more prone to stress-induced voiding. Stress migration tests verify that MTF values decrease with increasing line width. Modeling results are consistent with experimental findings, while providing more insightful understanding of stress-driven mechanisms in stress migration.

Stress modeling of Cu/low-k BEoL - application to stress migration

Stress migration (SM) or stress-induced voiding (SIV) experiments were conducted for two BEoL (Back End of Line) technologies: Cu/FTEOS and Cu/Low-k. Experiments have shown the mean time to failure (MTF) depends on ILD (interlayer dielectric) materials properties, ILD stack and metal line width. Stress migration is worse in Cu/low-k, manifesting as significantly reduced MTF under accelerated testing. Line width also has a more profound effect on stress migration reliability in Cu/low-k than in Cu/FTEOS. Wider lines produce higher failure rates, due to larger stress magnitudes in Cu and larger active diffusion volumes. Stress modeling using Finite Element Analysis (FEA) was performed to quantify the stress fields in the via-chain test structure used for SM reliability testing. In order to account for the effect of process steps on stress evolution, a process-oriented modeling approach was developed. Stress in the metal line is a function of ILD (inter-layer dielectric) properties, ILD stack and metal line width. The concept of a SM Risk Index is proposed to assess BEoL stress migration reliability from the stress perspective. Comparison of the SM Risk Index for Cu/FTEOS and Cu/low-k shows that the latter is more prone to stress induced voiding. Stress migration tests verify that MTF values decrease with increasing line width. Modeling results are consistent with experimental findings, while providing more insightful understanding of stress-driven mechanisms in stress migration.

Finite-element modeling and X-ray measurement of strain in passivated Al lines during thermal cycling

Narrow-pitch encapsulated Al lines are used as interconnect metallization in integrated circuits. The authors have measured the principal strain state of Al alloy lines passivated with silicon nitride directly as a function of temperature. They compare these results with calculations of the strain state in these lines using finite-element modeling. The measured strain-temperature behavior shows food fundamental agreement with finite-element modeling, although the magnitude of the strains measured with X-rays is less than that predicted by modeling due to voiding in the lines.

Extendibility of NiPt Silicide Contacts for CMOS Technology Demonstrated to the 22-nm Node

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach below 10^-8 Omega-cm² for both n⁺ and p⁺ Si and demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22 nm node.