Paul S. Fechner

Radiation hardened SOI CMOS and 1M SRAM

Describes 2M rad(SiO/sub 2/) radiation hardened partially depleted SOI CMOS technology used to fabricate a 1M SRAM on full dose SIMOX (Separation by IMplantation of OXygen) wafers with an oxygen ion dose of 1.7/spl times/10/sup 18//cm/sup 2/ at 190 keV. They were annealed by Honeywell at 1325 /spl deg/C resulting in buried oxide thickness of approximately 370 nm and post CMOS processing silicon thickness of approximately 190 nm. Prior to processing, the SIMOX wafers are screened to achieve surface defect density of <0.2 per cm/sup 2/, HF defect density of <1 per cm/sup 2/, and background doping of <2/spl times/10/sup 16/ per cm/sup 3/.

Bias dependence of buried oxide hardness during total dose irradiation

Direct correlation is reported between single-transistor back channel leakage and the anomalous increase in 16 K-SRAM standby current after total dose irradiation. 16 K-SRAMs fabricated on SIMOX (separation by implantation of oxygen) substrates were total-dose tested up to 10 Mrad (SiO/sub 2/) using an ARACOR X-ray source with zero substrate bias. Different bias conditions were examined to determine the worst case condition for the buried oxide. The worst bias condition for back channel buried oxide threshold voltage shift is when irradiated with zero substrate bias. The standby current hump of the 16 K-SRAM after total dose irradiation can be directly correlated with the NMOS transistor back channel leakage current. Reduction of standby current with increased total dose can be explained by the buildup of interface charge which reduces the back channel leakage.<<ETX>>