Paul S. Levy

Designing in power-down test circuits

Built-in self-test circuitry that is active only during testing is described. The benefit of these types of circuits is that defects that are not uncovered within the test circuitry will not contribute to failures in the hosts ICs. Thus, the overall reliability of the IC in its targeted application should increase. Also, since the test circuitry is inactive, there will be less overall power consumption. Layout issues, simulation models, and interface/isolation considerations are discussed. Some general design guidelines are given.<<ETX>>

Power-down integrated circuit built-in self-test structures

Built-in self-test structures composed of logic elements are isolated from the host circuitry by means of separate Test VDD, so that it appears as an open circuit during normal operation of the IC. The separate Test VDD is employed to re-configure the host circuit and operate the test circuitry in the test mode. When Test VDD is removed, the test circuit powers down and disconnects from the host becoming invisible to the normal operation of the IC.<<ETX>>

Power-down structures for BIST

The author discusses how power-down test structures use a separate test power supply to allow the associated test circuitry to power-down when not being tested. These structures are specially designed to self-isolate from the host circuit when power is removed from Tvdd. This action will increase reliability by removing auxiliary circuit elements used for test from the host design during normal operation and decrease power consumption.<<ETX>>