Paul Svasta

Investigations on assembling of electronic packages onto glass substrates using lead-free technology

In the last decade new materials were launched on the market. This is the case of PCB substrates, also. Requirements for improved heat transfer between power components and the solid metal base led to a new PCB technology, on copper and aluminum substrates. Typical applications are those where high level of heat has to be dissipated from the circuit (in LED applications, for example). Requirements for a very clean environment led to create PCBs on glass substrate. Typical applications are for medical instruments, products and devices. Addressing only to SMT issues, the new materials are a challenge for conventional assembling technologies. High thermal mass of the substrate makes impossible the IR and convection reflow assembling, especially since the lead-free technology raised the process temperature. In this case, Vapour Phase Soldering (VPS) technology seems to be the most appropriate for obtaining the best assembling results. Using VPS and having broad knowledge in the management of assembling technologies and Design For Manufacturing (DFM) represent the key of success in case of PCB products based on glass. The paper presents the applied research performed in an assembly line based on VPS equipment, in order to define the design requirements for assembling circuits on glass substrate. Even for electronic medical applications the RoHS European Directive is not yet mandatory, this work is useful for the future, when lead-free products will cover also this area of electronics.

Characterization of differential interconnects from time domain reflectometry measurements

Differential signaling schemes are a common approach to achieving higher noise immunity for critical signals in a high-speed digital design. A differential pair constitutes a set of coupled transmission lines and, therefore, can be modeled and simulated as such. Short differential lines can be modeled using coupled LC matrices, but a distributed model is required for longer lines. In this article, a technique for extracting such a distributed coupled line model from time domain reflectometry (TDR) measurements is presented. This model can be easily utilized in a SPICE simulator, making it extremely useful for high-speed differential interconnect modeling and simulation. The resulting accurate models help the designer to achieve a better understanding of the differential interconnects, resulting in higher performance system design.

Accurate 3D modelling and simulation of advanced packages and vertical stacked dice

In previous papers, the authors have investigated planar configurations existing in high-density interconnection (HDI) structures from the electromagnetic and signal integrity viewpoints (using 2.5D field solvers), offering solutions to signal integrity (SI) and electromagnetic compatibility (EMC) concerns . This paper presents new investigations and results focused on 3D modelling and simulation of advanced packages (SIP- system in package, SOP - system on package) and vertical stacked dice. A system-in-a-package or system in package, also known as a chip stack MCM, has a number of integrated circuits enclosed in a single package or module. The SIP performs all or most of the functions of an electronic system. System-on-package (SOP) is the new emerging system technology that goes beyond system-on-chip (SOC) and system-in-package (SIP) and forms the basis of all emerging digital convergent electronic and bio-electronic systems.

Cryptographic coprocessor for data integrity algorithms

In cryptography, for message/data integrity assurances, that are vital for a security product, are used Hash functions. The Hash algorithm is based on a one-way-function that maps an arbitrary-length data to a fixed-length output. This paper will present the usage of the newest hash algorithm SHA-3 - Keccak into an electronic module based on FPGA. This will work, along with an ARM Cortex-A9 microprocessor, as a cryptographic coprocessor. The implemented hardware solution significantly increased the computational speed of the signal data processing.

Evaluation of the effects of the layout design on the quality of surface mount boards

This paper presents part of the results obtained after conducting an experiment designed with the help of the Design of Experiments (DoE) method. The aim of this experiment is to evaluate the dependencies between the layout design and the production quality of surface mount (SMT) boards. A test board was specially designed to allow us to vary certain factors. The DoE method was used to plan the variation of these factors in order to see their influences on the responses. The responses analyzed until now are: number of tombstones, wetting area, stand-off and existence of solder balls. The test was performed with 108 boards, two stencils, three solder pastes and three thermal profiles. Preliminary results show very few tombstones and good wetting areas for all three solder pastes in case of convection reflow. The heights for all components were measured before and after soldering. The analysis of the values obtained for the same chip component reveals that the stand-off difference (as we defined it) has the smallest value when the pad width is smaller than standard. Thus, the influence of the layout design on the quality of SMT boards can be observed.

Pulsed behavior of polymer protection devices

Polymer protection devices are placed on circuit boards as chip devices to protect existing electronic devices from electrostatic discharge events (ESD). As there are no generally accepted standards for characterization of such devices, we used Transmission Line Pulsing (TLP) to determine trigger- and clamping- voltages as well as leakage currents. Using short duration pulses (less than 10 ns) from a Very-Fast Transmission Line Pulser (VF-TLP) gives information of the transient behavior during pulsing. The influence of the pulse width and amplitude on the current-voltage behavior was investigated on chip size polymer voltage suppressors.

Numerical processing of stereo optical images for autonomous navigation

Autonomous robots had been for a long time any engineers dream. First steps were done by creating robots able to move in well know space for restricted distances. The need of a robot able to navigate on an area with high irregularities and many unknowns obstacles lead to the organisation of the DARPA Grand Challenge. Most competitors used GPS and Laser Telemeters for terrain investigation. This paper is describing a different way to investigate the terrain topography: stereo images. This is the closest way of terrain investigation to the human sight. By gathering as much information from images the need for other sensors on the robot will be no more. This is an obvious fact since for human more than 90% of information about the surrounding environment is coming from sight. An equipment to capture and process stereo images had been build and the software was created to prove the accuracy of this method to detect and avoid obstacles and to investigate the terrain topography for uncharted areas. To extract the information needed for the navigation from the stereo optic images, complex algorithms of shape recognisance, pattern mach and cross correlation will be involved together with image calibration and sharpening. Because the processing power requirements will be huge methods to decrease the computation need will be used to increase the processing speed On site measurements will give a clear view of the performance and accuracy. For better measurements the stereo optical system will be backed up by other sensors: magnetic compass, gyroscopes, tri-axial accelerometers, pressure sensors, GPS and odometer. Some of these are redundant and are used just to confirm and improve the accuracy of the information gathered thru the stereo optical images.

Components' emissivity in reflow soldering process

Thermal processes encountered in surface mount assembly are very complex. Transferring heat between hot source (reflow oven) to assembly (printed circuit board, components and interconnecting alloy) is done through well known possibilities: convection, infrared radiation, conduction and phase changing. The convection and the IR radiation are the main ways to transfer heat from source to assembly. The conduction and the phase changing are secondary forms. They are very important to establish the uniform temperature distribution in an assembly. Modeling the four heat transfers in case of surface mount technology it is the necessarily to split the problem in two parts. First, the reflow oven must be modeled. Second, the assembly must be modeled. Since the model for the oven is known, the assembly could be different (in the same oven are passing through different equipped PCBs). The paper present some steps of assembly modeling in fact the capability of the assembly to take heat from the heat source(reflow oven) through IR radiation. For IR heat transfer the most important parameter is the emissivity of exposed surfaces. These surfaces are: heater sources, the SMD components, and the PCBs solder mask. Supposing heaters surface emissivity to be constant to know how the assembly will absorb the heat through IR, its necessary to know the emissivity of components, surfaces (and the emissivity of exposed PCB). The components emissivity usual is established by measurements. The method, measurements (including the corrections) and conclusions are presented in the paper.

Thermal limits in reflow soldering process

One of critical stage of surface assembly process is the thermal process that determines the phase changing of junction material (the solder paste or conductive adhesive). The equipment that does this treatment can transfer heat to assembly by convection, infrared radiation, or both. Each ones the dominant heat transfer inside the reflow oven, for some components (component’s manufacturer do it) in the last thermal zone (soldering zone), exist a maximum time and temperature to he not exceed. On the other hand, it exists a minimal product time-temperature to realize quality-soldering joints (from assembler point of view). To drive the process between these limits, some parameters of assembly must be previously evaluated. The assembly’s parameters tacking into account are the PCB thickness, the copper surface percentage, the vias density, the component density, the maximum thermal mass difference, and the light surface percentage. The goal of this paper is to emphasis the preliminary feedback that the assembler offers to improve quality designer purposes.

Advanced team work education within the concurrent engineering paradigm

Development of a large perspective for the e-global economy requires a new approach for learning and training processes. Corporate and governmental organizations are significantly shifting their strategies from hierarchical work structures, creating departmental layers, toward team-based flat organizations. These human centered holons may cut across responsibilities. Large transnational companies try to learn behavior as local citizens everywhere, whilst local SMEs try to learn how to operate in the global market. Local and regional economics are a source of innovative activity but competitiveness has to be global. Accordingly, with this trend of an e-activities based society, it is necessary to develop a new concept based on the concurrent engineering methodology involving team building and operation. The paper aims to launch a discussion about change management for a well balanced curriculum between traditional face to face classes and e-learning facilities. A case study for education in the field of electronic packaging is also presented.