Paul Voois

A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s

Multi-mode fibers (MMF) are typically used in LAN applications, in links which may reach or exceed 300 meters. Widespread use of electronic dispersion compensation (EDC) for MMF is prompted by the ratification of the 10GBASE-LRM standard. A number of studies have demonstrated the superiority of MLSD for this application. This paper describes an all-DSP single-chip 90nm CMOS MLSD-based EDC transceiver for MMF.

A 10.3GS/s 6bit (5.1 ENOB at Nyquist) time-interleaved/pipelined ADC using open-loop amplifiers and digital calibration in 90nm CMOS

A 10.3 GS/s ADC with 5 GHz input BW and 6 bit resolution in 90 nm CMOS is presented. The architecture is based on an 8 way interleaved/ pipelined ADC using open-loop amplifiers and digital calibration. The measured performance is 5.8 ENOB (36.6 dB SNDR) for a 100 MHz input signal and 5.1 ENOB (32.4 dB SNDR) for a 5 GHz input (Nyquist) with phase offset correction across the interleaved array.

A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at 10 Gb/s

This paper presents the architecture and circuit design of a single chip 32 mm2 90 nm CMOS DSP transceiver for electronic dispersion compensation (EDC) of multimode fibers at 10 Gb/s, based on maximum likelihood sequence detection (MLSD). This is the first MLSD-based transceiver for multimode fibers and the first fully integrated DSP based transceiver for optical channels reported in the technical literature. The digital receiver incorporates equalization, Viterbi detection, channel estimation, timing recovery, and gain control functions. The analog front-end incorporates an 8-way interleaved ADC with self-calibration, a programmable gain amplifier, a phase interpolator, and the transmitter. Also integrated are a XAUI interface, the physical coding sublayer (PCS), and miscellaneous test and control functions. Experimental results using the stressors specified by the IEEE 10 GBASE-LRM standard, as well as industry-defined worst-case fibers are reported. A sensitivity of - 13.68 dBm is demonstrated for the symmetric stressor in a line card application with a 6 inch FR4 interconnect.

A 40nm CMOS single-chip 50Gb/s DP-QPSK/BPSK transceiver with electronic dispersion compensation for coherent optical channels

Optical communication technology in long-haul and metropolitan links is experiencing a transition to coherent techniques and high spectral efficiency modulation formats such as dual-polarization (DP) QPSK, DP-QAM and OFDM. The combination of coherent demodulation and DSP allows costly optical signal-processing hardware used to compensate fiber optic impairments such as chromatic dispersion (CD) and polarization-mode dispersion (PMD) to be replaced by DSP-based techniques [1]. Economic large-scale deployment of coherent systems requires the integration of the optical transceiver functions in CMOS technology.

Architecture of a Single-Chip 50 Gb/s DP-QPSK/BPSK Transceiver With Electronic Dispersion Compensation for Coherent Optical Channels

The architecture of a single-chip dual-polarization QPSK/BPSK 50 Gigabits per second (Gb/s) DSP-based transceiver for coherent optical communications is presented. The receiver compensates the chromatic dispersion (CD) of more than 3,500 km of standard single-mode fiber using a frequency-domain equalizer. A time-domain four-dimensional MIMO transversal equalizer compensates up to 200 ps of differential group delay (DGD) and 8000 ps 2 of second-order polarization-mode dispersion (SOPMD). Other key DSP functions of the receiver include carrier and timing recovery, automatic gain control, channel diagnostics, etc. A novel low-latency parallel-processing carrier recovery implementation which is robust in the presence of laser phase noise and frequency jitter is proposed. The chip integrates the transmitter, receiver, framer and host interface functions and features a 4-channel 25 Gs/s 6-bit ADC with a figure of merit (FOM) of 0.4 pJ/conversion. Each ADC channel is based on an 8-way interleaved flash architecture. The DSP uses a 16-way parallel processing architecture. Extensive measurement results are presented which confirm the design targets. Measured optical signal-to-noise ratio (OSNR) penalty when compensating 200 ps DGD and 8000 ps 2 is 0.1 dB, while OSNR penalty when compensating 55 ns/nm CD (corresponding to 3,500 km of standard single-mode fiber) is 0.5 dB.

Standards Compliance Testing of Optical Transmitters Using a Software-Based Equalizing Reference Receiver

Incorporation of EDC technology in optical networking presents new challenges in developing tests for transmitter standards compliance. This paper describes the 10 GBASE-LRM TWDP test, recently adopted for 10 Gbps Ethernet links over dispersive multimode fiber.

Combination of InP MZM Transmitter and Monolithic CMOS 8-State MLSE Receiver for Dispersion Tolerant 10 Gb/s Transmission

We demonstrate that InP modulators together with 1 sample/bit MLSE gives equivalent performance to linear electro-optic Mach-Zehnder modulators combined with oversampled MLSE, potentially providing significant reduction in power dissipation and footprint.