Paulo Da Cunha Possa

FPGA-based hardware acceleration: A CPU/accelerator interface exploration

One of the main challenges for embedded system designers is to find a tradeoff between performance and power consumption. In order to reach this goal, hardware accelerators have been used to offload specific tasks from the CPU, improving the global performance of the system and reducing its dynamic power consumption. Enabling the use of accelerators could become a tricky task for embedded system designers. This paper presents a complete acceleration design flow for embedded systems with an exploration of different interfaces between CPU and accelerator, analyzing their performances, resources overhead, power consumption, and implementation methods.

A new self-adapting architecture for feature detection

In this paper, we present a FPGA based flexible self-adapting architecture for two features detectors, the Canny edge detector and the Harris corner detector, with reduced latency and memory requirements, and supporting variable resolution images. The new architecture uses neighbourhood extractors that can self-adapt its parameters on-the-fly and algorithm simplifications to reduce mathematical complexity, memory requirements and latency without losing reliability.

LP-P\(^2\)IP: A Low-Power Version of P\(^2\)IP Architecture Using Partial Reconfiguration

Power consumption reduction is crucial for portable equipments and for those in remote locations, whose battery replacement is impracticable. P\(^2\)IP is an architecture targeting real-time embedded image and video processing, which combines runtime reconfigurable processing, low-latency and high performance. Being a configurable architecture allows the combination of powerful video processing operators (Processing Elements or PEs) to build the target application. However, many applications do not require all PEs available. Remaining idle, these PEs still represent a power consumption problem that Partial Reconfiguration can mitigate. To assess the impact on energy consumption, another P\(^2\)IP implementation based on Partial Reconfiguration was developed and tested with three different image processing applications. Measurements have been made to analyze energy consumption when executing each of three applications. Results show that compared to the original implementation of the architecture use of Partial Reconfiguration leads to power savings of up to 45%.

Image and video processing on fpgas: An exploration framework for real-time applications

Abstract This work presents a design framework for real-time image and video processing enabling exploration and evaluation of different processing techniques. The goal of our educational approach is to develop a flexible and easily customizable environment for prototyping different processing techniques on Field Programmable Gate Arrays (FPGAs), targeting specific applications. In this paper we give an overview of different requirements and techniques of video processing featuring FPGAs. Three real-time video processing algorithms were combined to show the advantages and characteristics of our approach. Within the framework, the modules running in parallel can be easily swapped at run-time according to the application specific needs.

Design of a low latency spectrum analyzer using the Goertzel Algorithm with a Network on Chip

This paper presents the design of a Low latency spectrum analyzer targeted for Systems on Chip applications to perform real time multiband control. The discrete Fourier transforms are computed with the Goertzel Algorithm which performs better than the traditional FFT in our application case. The application is mapped on a Network on Chip. The complete design includes the scheduling, the mapping and the fine tuning of the NoC, which was performed with our Matlab NoC Simulation environment. The Goertzel algorithm dataflow makes it possible to use a broadcast type routing algorithm to reduce the traffic in the NoC. The results present the details of the design and reveal the parameters that can be adjusted to fine tune the Performance/Consumption tradeoff of the application.