Pawan Kapur

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

Technology and reliability constrained future copper interconnects. I. Resistance modeling

A realistic assessment of future interconnect performance is addressed, specifically, by modeling copper (Cu) wire effective resistivity in the light of technological and reliability constraints. The scaling-induced rise in resistance in the future may be significantly exacerbated due to an increase in Cu resistivity itself, through both electron surface scattering and the diffusion barrier effect. The impact of these effects on resistivity is modeled under various technological conditions and constraints. These constraints include the interconnect operation temperature, the effect of copper-diffusion barrier thickness and its deposition technology, and the quality of the interconnect/barrier interface. Reliable effective resistivity trends are established at various tiers of interconnects, namely, at the local, semiglobal, and global levels. Detailed implications of the effect of resistivity trends on performance are addressed in the second part of this work.

Power comparison between high-speed electrical and optical interconnects for interchip communication

An I/O bandwidth commensurate with a dramatically increasing on-chip computational capability is highly desirable. Achieving this goal using board-level copper interconnects in the future will become increasingly challenging owing to severe increase in high-frequency, skin-effect and dielectric loss, noise due to crosstalk, impedance mismatch, and package reflections. The solutions designed to overcome these deleterious effects require complex signal processing at the interconnect endpoints, which results in a larger power and area requirement. Optical interconnects offer a powerful alternative, potentially at a lower power. Prior work in comparing the two technologies has entailed overly simplified assumptions pertaining to either the optical or the electrical system. In this paper, we draw a more realistic power comparison with respect to the relevant parameters such as bandwidth, interconnect length and bit error rate (BER) by capturing the essential complexity in both types of interconnect systems. At the same time, we preserve the simplicity by using mostly analytical models, verified by SPICE simulations where possible. We also identify critical device and system parameters, which have a large effect on power dissipation in each type of interconnect, while quantifying the severity of their impact. For optical interconnect, these parameters are detector and modulator capacitance, responsivity, coupling efficiency and modulator type; whereas, in the case of electrical system, the critical parameters include receiver sensitivity/offset and impedance mismatch. Toward this end, we first present an optimization scheme to minimize optical interconnect power and quantify its performance as a function of future technology nodes. Next, on the electrical interconnect side, we examine the power dissipation of a state-of-the-art electrical interconnect, which uses simultaneous bidirectional signaling with transmitter equalization and on-chip noise cancellation. Finally, we draw extensive comparisons between optical and electrical interconnects. As an example, for bandwidth of 6 Gb/s at 100 nm technology node, lengths greater than the critical length of about 43 cm yields lower power in optical interconnects. This length becomes lower (making optics more favorable) with higher data rates and lower bit error rate requirement.

Technology and reliability constrained future copper interconnects. II. Performance implications

For pt. I see ibid., vol.49, no.4, pp.590-7 (2002). This work extends the realistic resistance modeling of on-chip copper interconnects to assess its impact on key interconnect performance metrics. As quantified in part I of this work, the effective resistivity of copper is not only significantly larger than its ideal, bulk value but also highly dependent on technology and reliability constraints. Performance is quantified under various technological conditions in the future. In particular, wire delay is extensively addressed. Further, the impact of optimal repeater insertion to improve these parameters is also studied using realistic resistance trends. The impact of technologically constrained resistance on power penalty arising from repeater insertion is briefly addressed. Where relevant, aforementioned results are contrasted with those obtained using ideal copper resistivity.

Performance Comparisons Between Carbon Nanotubes, Optical, and Cu for Future High-Performance On-Chip Interconnect Applications

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.

Power estimation in global interconnects and its reduction using a novel repeater optimization methodology

The purpose of this work is two fold. First, to quantify and establish future trends for the dynamic power dissipation in global wires of high performance integrated circuits. Second, to develop a novel and efficient delay-power tradeoff formulation for minimizing power due to repeaters, which can otherwise constitute 50% of total global wire power dissipation. Using the closed form solutions from this formulation, power savings of 50% on repeaters are shown with minimal delay penalties of about 5% at the 50 nm technology node. These closed-form, analytical solutions provide a fast and powerful tool for designers to minimize power.

A Highly Scalable Capacitorless Double Gate Quantum Well Single Transistor DRAM: 1T-QW DRAM

We propose a new kind of capacitorless DRAM: 1Transistor Quantum Well structure, which has a ldquostorage pocketrdquo for holes within the body. This memory gives the opportunity to engineer spatial hole distribution within the body of the device, which is not possible with the conventional 1T-DRAMs. Using this novel device, we demonstrate approximately two order-of-magnitude increase in the drain-current (Id) difference between the reads of two states of the memory.

Experimental characterization of single-walled carbon nanotube film-Si Schottky contacts using metal-semiconductor-metal structures

We demonstrate that single-walled carbon nanotube (CNT) films make a Schottky contact on silicon by experimentally characterizing metal-semiconductor-metal (MSM) structures. We find that at temperatures above 240K, thermionic emission is the dominant transport mechanism across CNT film-Si contacts, and at lower temperatures tunneling begins to dominate. At high bias voltages, the CNT film MSM devices exhibit a higher photocurrent-to-dark current ratio relative to that of metal control devices. Our results not only provide insight into the fundamental electronic properties of the CNT film-Si junction but also opens up the possibility of integrating CNT films as Schottky electrodes in conventional Si-based devices.

A very low temperature single crystal germanium growth process on insulating substrate using Ni-induced lateral crystallization for three-dimensional integrated circuits

Metal (Ni)-induced lateral crystallization (MILC) of amorphous (α)-germanium (Ge) films on silicon dioxide (SiO2) is investigated on α-Ge planar films, annealing at 350–380°C in a N2 ambient. MILC is not observed after annealing for 1h at 350°C, and self-nucleation with its small, deleterious microcrystals plagues the process at 380°C. 360°C is determined to be an optimum annealing temperature. These conditions are subsequently applied to a patterned nanowire to obtain a single-crystal Ge wire on SiO2. The method is promising for integrating high quality Ge transistors at low temperatures as required by three-dimensional integrated circuits.

A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM

We experimentally demonstrate and characterize a vertical (current flow that is perpendicular to the wafer) source (bottom)/drain (top) double-gate capacitorless single-transistor DRAM on a bulk silicon wafer. We have electrically measured retention times in excess of 25 ms. Device fabrication was facilitated by several key process innovations, which allow the device to also be integrated with planar devices using minimal additional process steps. The structure results in a highly scalable DRAM down to 22-nm technology node.