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Dive into the research topics where Pawel Gepner is active.

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Featured researches published by Pawel Gepner.


parallel computing in electrical engineering | 2006

Multi-Core Processors: New Way to Achieve High System Performance

Pawel Gepner; Michal Filip Kowalik

Multi-core processors represent an evolutionary change in conventional computing as well setting the new trend for high performance computing (HPC) - but parallelism is nothing new. Intel has a long history with the concept of parallelism and the development of hardware-enhanced threading capabilities. Intel has been delivering threading-capable products for more than a decade. The move toward chip-level multiprocessing architectures with a large number of cores continues to offer dramatically increased performance and power characteristics. Nonetheless, this move also presents significant challenges. This paper describes how far the industry has progressed and evaluates some of the challenges we are facing with multi-core processors and some of the solutions that have been developed


international conference on conceptual structures | 2011

Component Approach to Computational Applications on Clouds

Maciej Malawski; Jan Meizner; Marian Bubak; Pawel Gepner

Abstract Running computational science applications on the emerging cloud infrastructures requires appropriate programming models and tools. In this paper we investigate the applicability of the component model to developing such applications. The component model we propose takes advantages of the features of the IaaS infrastructure and offers a high-level application composition API. We describe experiments on a scientific application from the bioinformatics domain, using a hybrid cloud infrastructure which consists of a private cloud running Eucalyptus and the Amazon EC2 public cloud. The measured performance of virtual machine startup time and virtualization overhead indicate promising prospects for exploiting such infrastructures along with the proposed component-based approach.


Scientific Programming | 2015

Adaptation of MPDATA heterogeneous stencil computation to Intel Xeon Phi coprocessor

Lukasz Szustak; Krzysztof Rojek; Tomasz Olas; Lukasz Kuczynski; Kamil Halbiniak; Pawel Gepner

The multidimensional positive definite advection transport algorithm (MPDATA) belongs to the group of nonoscillatory forward-in-time algorithms and performs a sequence of stencil computations. MPDATA is one of the major parts of the dynamic core of the EULAG geophysical model. In this work, we outline an approach to adaptation of the 3D MPDATA algorithm to the Intel MIC architecture. In order to utilize available computing resources, we propose the (3 + 1)D decomposition of MPDATA heterogeneous stencil computations. This approach is based on combination of the loop tiling and fusion techniques. It allows us to ease memory/communication bounds and better exploit the theoretical floating point efficiency of target computing platforms. An important method of improving the efficiency of the (3 + 1)D decomposition is partitioning of available cores/threads into work teams. It permits for reducing inter-cache communication overheads. This method also increases opportunities for the efficient distribution of MPDATA computation onto available resources of the Intel MIC architecture, as well as Intel CPUs. We discuss preliminary performance results obtained on two hybrid platforms, containing two CPUs and Intel Xeon Phi. The top-of-the-line Intel Xeon Phi 7120P gives the best performance results, and executes MPDATA almost 2 times faster than two Intel Xeon E5-2697v2 CPUs.


international conference on computational science | 2008

Second Generation Quad-Core Intel Xeon Processors Bring 45 nm Technology and a New Level of Performance to HPC Applications

Pawel Gepner; David L. Fraser; Michal Filip Kowalik

The second generation of Quad-Core Intel® Xeon® processors was launched on November 12th 2007. In this paper we take a look at what the new 45 nm based Quad-Core Intel Xeon Processor brings to high performance computing. We compare an Intel Xeon 5300 series based system with a server utilizing his successor the Intel Xeon 5400. We measure both CPU generations operating in dual socket platforms in typical HPC benchmark scenario using some common HPC benchmarks. The results presented clearly show that the new Intel Xeon processor 5400 family provides significant performance advantage on typical HPC workloads and would therefore be seen to be an appropriate choice for many of HPC installations.


international conference on parallel processing | 2013

Using Intel Xeon Phi Coprocessor to Accelerate Computations in MPDATA Algorithm

Lukasz Szustak; Krzysztof Rojek; Pawel Gepner

The multidimensional positive definite advection transport algorithm (MPDATA) belongs to the group of nonoscillatory forward-in-time algorithms, and performs a sequence of stencil computations. MPDATA is one of the major parts of the dynamic core of the EULAG geophysical model.


international multiconference on computer science and information technology | 2010

Use of hybrid recursive CSR/COO data structures in sparse matrix-vector multiplication

Michele Martone; Salvatore Filippone; Salvatore Tucci; Pawel Gepner; Marcin Paprzycki

Recently, we have introduced an approach to basic sparse matrix computations on multicore cache based machines using recursive partitioning. Here, the memory representation of a sparse matrix consists of a set of submatrices, which are used as leaves of a quad-tree structure. In this paper, we evaluate the performance impact, on the Sparse Matrix-Vector Multiplication (SpMV), of a modification to our Recursive CSR implementation, allowing the use of multiple data structures in leaf matrices (CSR/COO, with either 16/32 bit indices).


international symposium on parallel and distributed computing | 2010

Early Performance Evaluation of New Six-Core Intel® Xeon® 5600 Family Processors for HPC

Pawel Gepner; Michal Filip Kowalik; David L. Fraser; Kazimierz Wackowski

In this paper we take a look at what the newest member of the Intel Xeon Processor family, code named Westmere brings to high performance computing. We compare three generations of Intel Xeon based systems and present a performance evolutions based on 16 node clusters based on these CPUs respectively. We compare CPU generations utilizing dual socket platforms and a cluster across a number of HPC benchmarks and focused on different performance field and aspect. We will evaluate also technologies and features like Intel’s Hyper Threading Technology (HT) and Intel Turbo Boost Technology (Turbo Mode) and the performance implication of these technologies for HPC.


international conference on parallel processing | 2013

Elliptic Solver Performance Evaluation on Modern Hardware Architectures

Milosz Ciznicki; Michal Kulczewski; Krzysztof Kurowski; Pawel Gepner

The recent advent of novel multi- and many-core architectures forces application programmers to deal with hardware-specific implementation details and to be familiar with software optimisation techniques to benefit from new high-performance computing machines. An extra care must be taken for communication-intensive algorithms, which may be a bottleneck for forthcoming era of exascale computing. This paper aims to present performance evaluation of preliminary adaptation techniques to hybrid MPI+OpenMP parallelisation schemes we provided into the EULAG code. Various techniques are discussed, and the results will lead us toward efficient algorithms and methods to scale communication-intensive elliptic solver with preconditioner, including GPU architectures to be provided later in the future.


federated conference on computer science and information systems | 2015

InterCriteria Analysis of a model parameters identification using genetic algorithm

Olympia Roeva; Peter Vassilev; Stefka Fidanova; Pawel Gepner

In this paper we apply an approach based on the apparatus of the Index Matrices and the Intuitionistic Fuzzy Sets - namely InterCriteria Analysis. The main idea is to use the InterCriteria Analysis to establish the existing relations and dependencies of defined parameters in non-linear model of an E. coli fed-batch cultivation process. Moreover, based on results of series of identification procedures we observe the mutual relations between model parameters and considered optimization techniques outcomes, such as execution time and objective function value. Based on InterCriteria Analysis we examine the obtained identification results and discuss the conclusions about existing relations and dependencies between defined, in terms of InterCriteria Analysis, criteria.


international conference on conceptual structures | 2011

Parallel application benchmarks and performance evaluation of the Intel Xeon 7500 family processors

Michal Kulczewski; Krzysztof Kurowski; Tomasz Piontek; Pawel Gepner; Mariusz Puchalski; Jacek Komasa

Abstract With the recent advent of novel multi- and many-core hardware architectures, application programmers have to deal with many hardware-specific implementation details and have to be familiar with software optimization techniques to benefit from new high-performance computing machines. Highly effcient parallel application design is in fact an interdisciplinary process involving domain specific and IT experts. Therefore, this paper aims to present early experiences with computationally demanding applications, development efforts and evaluation of their performance on the new family of Intel Xeon 7500 processors. We selected two application benchmarks applicable to real quantum chemistry and Computational Fluid Dynamics (CFD) problems as they can potentially take advantage of parallel processing on novel hardware architectures and built-in new features. Additionally, we discuss various parallel software improvements to mentioned applications, including appropriate changes to data structures as well as to communication and synchronization routines to deal with multi-level parallelism and hybrid hardware architectures. The obtained results confirmed that new hardware solutions can improve the overall application performance. However, in order to obtain a high level of parallel scalability various application modifications and tuning procedures are required as hardware configurations, including processors characteristics, interconnects and topologies, and they have a great influence on large-scale simulations.

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Marcin Paprzycki

Polish Academy of Sciences

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Maria Ganzha

Warsaw University of Technology

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Ivan Lirkov

Bulgarian Academy of Sciences

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Olympia Roeva

Bulgarian Academy of Sciences

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Stefka Fidanova

Bulgarian Academy of Sciences

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Tomasz Olas

Częstochowa University of Technology

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