Pedro Echeverría

FPGA Gaussian random number generator based on quintic hermite interpolation inversion

In this work we present a very accurate floating point FPGA implementation of a Gaussian random number generator (GRNG) based on the inversion method. The inverse Gaussian cumulative distribution function (GCDF-1) is approximated using a quintic degree segment interpolation with Hermite coefficients and an accuracy-adaptative segmentation which divides the GCDF-1 into several non-uniform segments. Our architecture generates simple floating point samples of 32 bits with an accuracy of 20 bits of mantissa, achieving a 185 MHz speed and a throughput of one sample per cycle on a Xilinx Virtex-II FPGA.

Floating-Point Exponentiation Units for Reconfigurable Computing

The high performance and capacity of current FPGAs makes them suitable as acceleration co-processors. This article studies the implementation, for such accelerators, of the floating-point power function xy as defined by the C99 and IEEE 754-2008 standards, generalized here to arbitrary exponent and mantissa sizes. Last-bit accuracy at the smallest possible cost is obtained thanks to a careful study of the various subcomponents: a floating-point logarithm, a modified floating-point exponential, and a truncated floating-point multiplier. A parameterized architecture generator in the open-source FloPoCo project is presented in details and evaluated.

A banked precomputation-based CAM architecture for low-power storage-demanding applications

The content-based access of CAMs makes them of great interest in look-up based operations. However, the large amounts of parallel comparisons required cause an expensive cost in power dissipation. In this work we present a novel banked pre-computation based architecture for low-power and storage-demanding applications. Experimental results show that the proposed banked architecture reduces up to a 76% of power consumption during the search process and decreases the active area in a 10% while performance is also improved by a 25%

High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator

Mersenne Twister (MT) uniform random number generators are key cores for hardware acceleration of Monte Carlo simulations. In this work, two different architectures are studied: besides the classical table-based architecture, a different architecture based on a circular buffer and especially targeting FPGAs is proposed. A 30% performance improvement has been obtained when compared to the fastest previous work. The applicability of the proposed MT architectures has been proven in a high performance Gaussian RNG.

Customizing floating-point units for FPGAs: Area-performance-standard trade-offs

Abstract The high integration density of current nanometer technologies allows the implementation of complex floating-point applications in a single FPGA. In this work the intrinsic complexity of floating-point operators is addressed targeting configurable devices and making design decisions providing the most suitable performance-standard compliance trade-offs. A set of floating-point libraries composed of adder/subtracter, multiplier, divisor, square root, exponential, logarithm and power function are presented. Each library has been designed taking into account special characteristics of current FPGAs, and with this purpose we have adapted the IEEE floating-point standard (software-oriented) to a custom FPGA-oriented format. Extended experimental results validate the design decisions made and prove the usefulness of reducing the format complexity.

An FPGA Run-Time Parameterisable Log-Normal Random Number Generator

Monte Carlo financial simulation relies on the generation of random variables with different probability distribution functions. These simulations, particularly the random number generator (RNG) cores, are computationally intensive and are ideal candidates for hardware acceleration. In this work we present an FPGA based Log-normal RNG ideally suited for financial Monte Carlo simulations, as it is run-time parameterisable and compatible with variance reduction techniques. Our architecture achieves a throughput of one sample per cycle with a 227.6 MHz clock on a Xilinx Virtex-4 FPGA.

Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach

In this work we present how variance reduction techniques can be applied to Monte Carlo simulations on an FPGA platform. Variance reduction techniques improve the accuracy of Monte Carlo simulations without increasing the number of individual simulations required, and consequently, the time and resources needed. Two techniques, Stratified Sampling and Latin Hypercube, have been implemented with a parameterizable architecture that additionally allows different configurations. To verify the proposed approach we have integrated these techniques on an FPGA Gaussian Random Number Generator, obtaining a complete a hardware accelerator for Monte Carlo simulations.

Designing highly parameterized hardware using xHDL

Current submicron technologies allow a very high degree of integration, resulting in incredibly complex designs implemented in a single chip. The task of the hardware designer is every day more complicated since the data and parameters involved in a design are wider and with increasing complexity in the interfaces. Modular design is needed to deal with these large, regular and repetitive structures. With this purpose the meta-language xHDL was conceived, providing flexible and friendly mechanisms for component parameterization, customization, instantiation and interconnection. In this paper two case studies will be analyzed in depth to illustrate the advantages of using xHDL. Based on the lessons learnt when specifying the case studies the meta-language has been extended to deal with new advanced features such as instantiation of external VHDL components and automatic generation of libraries of components.

Leakage Energy Reduction in Banked Content Addressable Memories

The content-based access of CAMs makes them of great interest in look-up based operations. However, the large amounts of parallel comparisons required cause an expensive cost in power dissipation. In this work we present a novel banked pre-computation based architecture for low-power and storage-demanding applications where the reduction of both dynamic and leakage power consumption is addressed. Experimental results show that the proposed banked architecture reduces up to an 89% of dynamic power consumption during the search process while the leakage power consumption is also minimized by a 90%. The active area is decreased in a 10% while performance is also improved by a 70%.

Experimental methodology for power characterization of FPGAs

This paper presents an experimental methodology for power characterization of FPGAs. The approach provides a good trade-off among characterization time, cost and accuracy. Our solution is based on the use of an embedded power integrator built upon a low cost controller that provides accumulated power data over fixed time periods. Experimental results have shown suitability of the proposed methodology for different power characterization scenarios.