Peng Junjie

Management of many data bits in ternary optical computers

Numerous data bits is one outstanding feature of ternary optical computers. How to effectively manage these data bits is a new topic in computer science. This paper forms a data bits management theory and technical framework through inheriting, updating, supplementing, and searching the research achievements in this field. The framework includes the following basic concepts and techniques. 1) “Calculating path” and “calculating channel” are the units of data bit management. The calculating path is used for simple data types and the channel for composite data types. 2) “Index of calculation amount” categorizes the scale of a task. Large, medium and small scale tasks will be managed with different strategies. 3) “Physical forms of data bits” identifies the devices occupied by data bits in each link of a data transmission. 4) A technique of “replacing an effectively lost data bit” will replace all disabled data bits with reserved redundancy data bits in a timely manner. Incidentally, the ternary optical computer has tolerant capability for software and hardware faults in data bits. 5) “Overall reconfiguring” reduces the number of reconfiguring actions that interrupt computing, by reconfiguring all the data bits at regular times. 6) “Data bits distribution technique” will employ different schemes for each scale task when distributing data bits. This paper also records the guidelines in the theory for designing a third generation experimental system for a ternary optical computer, named the SD11. The design goal of this experimental system is to research the applications of ternary optical computers. In SD11, a fundamental unit of the optical processor has 1024 data bits and 128 redundant bits, and one optical processor can possess 16 fundamental units in all. Thus, at most, one SD11 can have 16384 data bits and 2048 redundancy bits.

Implementation of parallel FFT algorithm on a ternary optical computer

The Fast Fourier Transform (FFT) is widely used in modern digital signal processing systems. In order to improve the efficiency of FFT, parallel methods are often used to speed up FFT in high-speed real-time application environments. However, due to the restrictions of size, energy consumption, heat dissipation etc., traditional electronic methods are becoming unsuitable for FFT applications in certain areas, such as aviation, aerospace, etc. Due to its characteristics of a massive number of data bits and low energy consumption, the Ternary Optical Computer (TOC) is a potential solution for these special cases. To verify this possibility, we studied the design and implementation of a high-speed parallel FFT on a TOC. Through analysis of the traditional radix-2, radix-4, and radix-8 DIT FFT operation processes, several FFT algorithms with higher parallelism, implemented on TOC, are designed by taking advantage of the characteristics of TOC. The implementation processes of these algorithms and the differences between them are presented. Meanwhile, the clock cycles and hardware resources required for each algorithm are also discussed. Simulation results reveal that the FFT implementation method is accurate. The algorithms require less power and fewer clock cycles when implemented on a TOC compared to the traditional methods implemented on an FPGA. This provides a new possible solution for high-speed low-power FFT implementation.

Structure and theory of dual-space storage for ternary optical computer

A ternary optical processor can have thousands of data bits, each of which can be independently assigned to a different task and reconstructed in real-time according to user demand at runtime. Consequently, significant amounts of data are frequently transferred between storage and processor in a ternary optical computer. In this study, a dual-space storage (DSS) system and a new technique to push memory space (PMS) on the DSS was developed to rectify this issue. The developed methods exploit the non-volatility and random access of solid state disks. This paper introduces the theory, architecture, management, and usage of DSS in detail, and also describes the hardware structure, technical principles, and push commands of PMS. Several new methods based on the unclosable windows in DSS (such as jobs resuming as soon as the computer is powered on, elimination of the wait time to launch a program, and improved system security) are also discussed. The results of simulation of DSS and PMS in an 8086 system verify the efficacy of the new theory and the related technologies. Both DSS and PMS not only meet the memory requirements of the ternary optical computer, but also provide a theoretical and technical foundation for constructing a new computer architecture based on solid state disks.

One-step binary MSD adder for ternary optical computer

On the basis of the research in MSD adder of Ternary Optical Computer (TOC), further work is carried out in one-step MSD adder with restricted input symbols. In this paper, the principle of general one-step MSD adder is introduced briefly. The core part of the principle can be reduced to the new conceptions of mid-bit transform, mid-bit transform table (MTT) and mid-bit transform unit (MTU). By restricting the input symbols, a simplified mid-bit transform table is obtained. Through the deep analysis to the simplified MTT, the subtransforms V and U as well as the main transform of the mid-bit transform are obtained, and the corresponding optical graphs are designed. Based on these, the structure of one-step MSD adder with restricted input symbols is proposed and its structure is designed. The software simulation and experiment to the mid-bit transform and the one-step adder show that the designed one-step MSD adder is effective. The adder will be one of the basic components of the ternary optical computer.