Pertti K. Ikalainen

High linearity power X-band GaInP/GaAs heterojunction bipolar transistor

We report for the first time two-tone test results measured on a GaInP/GaAs HBT. A 2/spl times/400 /spl mu/m/sup 2/ device delivered more than 1.3 W under one-tone testing at 7.5 GHz and output more than 1 W under two-tone. The corresponding intermodulation product is -14 dBc, and decreases to -21 and -36 dBc, respectively, at 3-dB and 10-dB back-off from the saturated two-tone output. These results demonstrate that GaInP/GaAs HBTs are suitable for microwave transmitter applications.<<ETX>>

Novel HBT with reduced thermal impedance

Heterojunction bipolar transistors have been fabricated using a novel process in which the majority of the front side of the chip is metallized to serve as the groundplane. The completed chip is assembled inverted so that the emitters are next to the heat sink; base and collector are contacted using through-wafer vias and microstrip lines on the back side of the chip. These devices show a 50% reduction in thermal impedance compared to conventionally fabricated devices and have achieved power densities of 10 W/mm of emitter length. Such devices are expected to have substantially lower emitter inductance as well, which may lead to improved gain at higher frequencies. >

Extraction of device noise sources from measured data using circuit simulator software

A procedure is presented for extracting the properties of device noise sources from experimental data. The extraction procedure can be implemented using commercially available circuit simulators. An example concerning a low-noise pseudomorphic high-electron-mobility transistor (HEMT) shows that the two noise sources extracted from experimental data are largely uncorrelated provided that parasitic elements are de-embedded from the measurement and that the sources are extracted in H-parameter format. >

20 W linear, high efficiency internally matched HBT at 7.5 GHz

An internally matched HBT has been developed for use in communications systems. An output power of 20 W with 6.5 dB gain and 40% PAE at 7.5 GHz was achieved. Over the 7.25 to 7.75 GHz band minimum output power was 16.5 W with minimum 38% PAE. Two tone testing showed good linearity.<<ETX>>

Low-noise, low DC power linear amplifiers

Low-noise, low-DC-power linear amplifiers using high-dynamic-range GaAs/int FETs are discussed. Noise figures as low as dB have been achieved in a Ku-band amplifier simultaneously with over 36-dBm OIP3 and 18-dB gain with only 655 mW of DC power. A wideband distributed amplifier has shown average midband 7-dB gain and noise figure together with 37-dBm OIP3 with 800 mW of DC power. Greatly improved second-order intercept points (OIP2) have been observed in the distributed amplifier as compared to typical ion-implanted MESFET amplifiers. A dual-gate version, of the distributed amplifier demonstrated significant dynamic range advantages over its ion-implanted FET counterpart. Overall, state-of-the-art results in terms of simultaneous linearity, noise figure, gain-bandwidth, and DC power consumption have been achieved.<<ETX>>

Low-Noise, Low DC Power Linear FET

A two-tone third-order output intercept point (OIP3) of 45 dBm has been achieved at 10 GHz with a 280-¿m GaAs MBE FET using only 248 mW of DC bias giving an OIP3/Pdc ratio of 128. Noise figure at that bias and tuning was 3.23 dB. Minimum noise figure of the same device was 1.43 dB.

Dynamic-range figure of merit in high-gain amplifiers

An optimum scaling that maximizes the (output and input) two-tone third-order intercept point of an amplifier with respect to DC power consumption is derived. The expression for spurious-free dynamic range of a high-gain amplifier is factored to separate effects of device parameters on dynamic range and to derive a new figure of merit. Based on this figure, the low-noise, linearized pulse-doped FET is judged to be the best high-dynamic-range device.<<ETX>>

Reply to "Comparison of thermal-shunt and flip-chip HBT thermal impedances: comment on novel HBT with reduced thermal impedance"

For the original article see ibid., vol. 5, no. 11, p. 373-5 (1995). As indicated in the aforementioned work, reducing thermal impedance is a key to increasing heterojunction bipolar transistor (HBT) power densities and there are several competing technologies evolving to reduce the thermal impedance of HBTs. This comment specifically addresses the question: does the flip-chip technology proposed by D. Hill et al. offer significantly lower HBT thermal impedance than the thermal-shunt technology? The commenters conclude that while any further reduction of the thermal impedance associated with flip-chip technology has yet to be determined, a comparison of the two technologies provides no compelling reason for adopting flip-chip technology.We would like to take this opportunity to respond to the above comment by Jenkins et al., who raised some good points that we would like to address concerning out letter. However, the primary point of their comment is to question whether flip-chip heterojunction bipolar transistors (HBTs) offer any advantage over the thermal-shunt technology developed by Bayraktaroglu et al. This question has been answered unambiguously in a recent report by Bayraktaroglu et al. that directly compared the thermal resistance of thermal-shunt and flip-chip devices. In this report, flip-chip devices on the average had 37% lower thermal resistance compared to conventional thermally shunted devices of similar size.