Peruvemba S. Balasubramanian

Subanosecond pixel rendering with million transistor chips

The desire for higher performance and higher resolution continuously increases the pixel update rates needed in high performance graphics systems. The increasing density of memory chips on the other hand reduces the pixel update rate that can be provided by the frame buffer. We present the design of a VLSI chip and a graphics system that can sustain sub-nanosecond pixel rendering rates for three-dimensional polygons and can be used to render about a million Z-Buffered and Gourard shaded polygons per second. The chip has been designed at the IBM Research Divisions Thomas J. Watson Research Center.

A million transistor systolic array graphics engine

Pixel processing is the most fundamental performance bottleneck in high-end three-dimensional graphics systems. This paper presents the design of a specialized custom VLSI graphics chip that was implemented with one million transistors and is capable of processing pixels at extremely rapid rates close to one nanosecond. This was made possible by utilizing a large number of identical pipelined pixel processors that operate in a purely systolic fashion. The chip has been designed at the IBM Research Divisions Thomas J. Watson Research Center.