Peter A. Ivey

An Ultra-high Speed Public Key Encryption Processor

This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of512 bits. The chip, which is 6.2 by 4.2 millimetres, has been designed in a 0.7 micron CMOS, silicon on insulator process and has a target clock speed of 15OMHz. It is a self contained subsystem which interfaces directly to standard microprocessors and will be capable of encrypting at rates well in excess of 64k baud (for contractural reasons we are unable, at this time, to disclose the emct speed of operation).

Design and evaluation of an epoxy three-dimensional multichip module

A low-cost, three-dimensional multichip module (MCM) technology provides greatly improved system density and reduced mass over planar packaging technologies. The technology offers a high degree of testability that negates the need for known good die (KGD) procurement. Testing is achieved with very low cost overheads and with no increase in the volume of the module. The technology allows complete, heterogeneous systems to be packaged and interconnected in a single, ultra-dense module. The electrical characteristics of the technology are comparable to standard chip packages. However, the parasitics due to package-to-package interconnects are eliminated. This removes the dominant cause of parasitics, dramatically improving the electrical characteristics. A programmable integrated camera and image processing system has been developed which incorporates a grayscale camera, analog-to-digital conversion, four programmable processors and memory. Utilizing the three-dimensional multichip module technology, the system, which consists of nine chips and 36 discrete components, has an overall volume of 4.77 ml. This is approximately six times more dense than an advanced PCB implementation. The system forms the first stage in the design and manufacture of a portable video communications device. For such applications, low system volume and mass are key attributes. The system demonstrates the potential of the packaging technique for the integration of complete mixed signal systems incorporating sensors and processing. Further developments to the technology will provide increased module density, improved routing capacity, and electrical performance.

Defect tolerant SRAM based FPGAs

We propose a new approach to redundancy for field programmable gate arrays (FPGAs) which uses a novel reconfiguration network. Modifications are made to the wiring segments and a spare element is incorporated at the end of each row. By using the technique it will be possible to construct arrays 10 times larger than are commercially economic at present. The scheme is applicable to any SRAM based FPGA and keeps full software compatability with existing design tools.<<ETX>>

A single-chip public key encryption subsystem

A single chip system (figure 1) capable of encryption using the Rivest, Shamir and Adleman (RSA) algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 micron technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.

A single chip video signal processing architecture for image processing, coding, and computer vision

A new VLSI (CMOS) architecture for an internally multiprocessing, single chip, SIMD-based video signal processor (VSP) is presented. The limitations of extended DSP architectures and conventional array processors are discussed in the context of image processing, coding and computer vision. How this gives rise to the architecture is described. Architectural flexibility is provided by the integration of a novel array-based processing core, together with a RISC processor, intelligent memory interface processor, and internal cache RAM. The array core architecture is a second generation, enhanced array whose key features are: 2 b datapath, dual processor mesh-connected array planes and combined SIMD/systolic functionality. The core is optimized for 2-D windowed operations, particularly 2-D multiply-accumulation and transforms. The device is expected to operate at 80 MHz on low voltage silicon and deliver real-time performance across a range of target applications. >

Nonplanar photolithography with computer-generated holograms.

We outline a method for accomplishing photolithography on grossly nonplanar substrates. First we compute an approximation of the diffraction pattern that will produce the desired light-intensity distribution on the substrate to be patterned. This pattern is then digitized and converted into a format suitable for manufacture by a direct-write method. The resultant computer-generated hologram mask is then used in a custom alignment tool to expose the photoresist-coated substrate. The technique has many potential applications in the packaging of microelectronics and microelectromechanical systems.

A method for processing laser speckle images to extract high-resolution motion

A method of processing speckle images in order to extract motion is presented which relies on the use of low-cost and local pixel computations. An analysis of the extraction process is also given, permitting error estimation and corrective post processing of the motion vectors obtained.

An ultra compact, low-cost, complete image-processing system

A low-cost, three-dimensional MCM technology, referred to as MCM-Vertical, or MCM-V gains an order of magnitude improvement in the volume efficiency of a system. An integrated camera and image-processing system forms the core module for a portable video communications system that could transmit compressed video over personal communications networks, such as GSM.

Silicon-on-insulator (SOI): A High Performance ASIC Technology

This paper describes the design of a 50,000 gate data encryption chip in a 0.7micron Silicon-on-Insulator CMOS technology and compares it to the same chip &signed in a 0.7 micron bulk CMOS process. The portability between rhe two processes has been carefully considered and the pe@ormance compared. SOI is found toperform50% faster, consume 30% less power and occupy approximately the same area as the bulk device.

Fabrication of a 3D electrically small antenna using holographic photolithography

We describe the novel fabrication of a 3D electrical small antenna and its subsequent characterization. The patterning of meander lines conformed onto a hemispherical substrate is achieved by 3D holographic photolithography, which uses time-division multiplexing of a series of iteratively optimized computer-generated holograms. The meander lines have a line width of 100 µm and line separation of 400 µm, with a line pitch of 500 µm and a total meander length of 145 mm. The working frequency is found to be 2.06 GHz, with an efficiency of 46%. This work demonstrates a new method for the fabrication of 3D conformal antennas.