Péter Arató

Hardware-software partitioning in embedded system design

One of the most crucial steps in the design of embedded systems is hardware-software partitioning, i.e. deciding which components of the system are implemented in hardware and which ones in software. Different versions of the partitioning problem are defined, corresponding to real-time systems, and cost-constrained systems, respectively. The authors provide a formal mathematic analysis of the complexity of the problems: it is proven that they are NP-hard in the general case, and some efficiently solvable special cases are also presented. An ILP (integer linear programming) based approach is presented that are solving the problem optimally even for quite big systems, and a genetic algorithm (GA) that finds near-optimal solutions for even larger systems. A specialty of the GA is that nonvalid individuals are also allowed, but punished by the fitness function.

Algorithmic aspects of hardware/software partitioning

One of the most crucial steps in the design of embedded systems is hardware/software partitioning, that is, deciding which components of the system should be implemented in hardware and which ones in software. Most formulations of the hardware/software partitioning problem are NP-hard, so the majority of research efforts on hardware/software partitioning has focused on developing efficient heuristics.This article considers the combinatorial structure behind hardware/software partitioning. Two similar versions of the partitioning problem are defined, one of which turns out to be NP-hard, whereas the other one can be solved in polynomial time. This helps in understanding the real cause of complexity in hardware/software partitioning. Moreover, the polynomial-time algorithm serves as the basis for a highly efficient novel heuristic for the NP-hard version of the problem. Unlike general-purpose heuristics such as genetic algorithms or simulated annealing, this heuristic makes use of problem-specific knowledge, and can thus find high-quality solutions rapidly. Moreover, it has the unique characteristic that it also calculates lower bounds on the optimum solution. It is demonstrated on several benchmarks and also large random examples that the new algorithm clearly outperforms other heuristics that are generally applied to hardware/software partitioning.

Finding optimal hardware/software partitions

Abstract Most previous approaches to hardware/software partitioning considered heuristic solutions. In contrast, this paper presents an exact algorithm for the problem based on branch-and-bound. Several techniques are investigated to speed up the algorithm, including bounds based on linear programming, a custom inference engine to make the most out of the inferred information, advanced necessary conditions for partial solutions, and different heuristics to obtain high-quality initial solutions. It is demonstrated with empirical measurements that the resulting algorithm can solve highly complex partitioning problems in reasonable time. Moreover, it is about ten times faster than a previous exact algorithm based on integer linear programming. The presented methods can also be useful in other related optimization problems.

Time-constrained scheduling of large pipelined datapaths

This paper addresses the most crucial optimization problem of high-level synthesis: scheduling. A formal framework is described that was tailored specifically for the definition and investigation of the time-constrained scheduling problem of pipelined datapaths. Theoretical results are presented on the complexity of the problem. Moreover, two new heuristic algorithms are introduced. The first one is a genetic algorithm, which, unlike previous approaches, searches the space of schedulings directly. The second algorithm realizes a heuristic search using constraint logic programming methods. The performance of the proposed algorithms has been evaluated on a set of benchmarks and compared to previous approaches.

Extending component-based design with hardware components

In order to cope with the increasing complexity of system design, component-based software engineering advocates the reuse and adaptation of existing software components. However, many applications--particularly embedded systems--consist of not only software, but also hardware components. Thus, component-based design should be extended to systems with both hardware and software components.Such an extension is not without challenges though. The extended methodology has to consider hard constraints on performance as well as different cost factors. Also, the dissimilarities between hardware and software (such as level of abstraction, communication primitives, etc.) have to be resolved.In this paper, the authors propose such an extended component-based design methodology to include hardware components as well. This methodology allows the designer to work at a very high level of abstraction, where the focus is on functionality only. Non-functional constraints are specified in a declarative manner, and the mapping of components to hardware or software is determined automatically based on those constraints in the so-called hardware/software partitioning step.Moreover, a tool is presented supporting the new design methodology. Beside automating the partitioning process, this tool also checks the consistency between hardware and software implementations of a component.The author also present a case study to demonstrate the applicability of the outlined concepts.

A high-level datapath synthesis method for pipelined structures

Abstract This paper presents a model and a method for the high-level datapath synthesis of pipelined ASIC architectures, starting with a behavioural description of the system consisting of theoretical operational units with arbitrary operation duration. The method calculates the minimal number of buffers to be inserted, optimally selects the number of types of additional operational units, and determines the minimal number of required copies. The aim of the procedure is to ensure a latency which can be given in advance, and could not be achieved without additional buffers and extra copies of the operational units. The method provides a solution to the resource allocation problem by establishing a compatibility relation between the concurrent operations. The constraints for the types of processors to be applied can vary, depending upon the hardware resources.

A Modified Inertial Method for Loop-free Decomposition of Acyclic Directed Graphs

Abstract Graph decomposition is a key process in system-level synthesis, even if it is used for allocation (e.g. hardware-software partitioning) or simple decomposition as a preprocessing step (e.g. for pipelining). Acyclic graphs are usually desirable in the design processes, thus preserving the acyclicity during decomposition is crucial. We propose a modified inertial decomposition to create loop-free decomposition results. We assign coordinates to the nodes based on their maximal distance from the inputs, and give an algorithm that finds the required number of cuts in polynomial time while balancing the size of segments and looking for minimal number of edges along cuts.

A data flow graph generation method starting from c description by handling loop nest hierarchy

The system-level synthesis of complex hardware or multiprocessing systems starts from some kind of a task description formalized usually in a high-level programming language. For this purpose, the C language is used very often. The further steps of the synthesis procedure are based on some kind of data flow graph representation of the task. Therefore, transforming C-code into a graph representation (as systematic as possible) is crucial step in the whole synthesis procedure. One of the difficulty in formalizing transformation algorithm is that the C-code may contain nested loops. The existing solutions suffer from the difficulty of handling such loop nest hierarchy. We present a method, which can solve systematically the transformation from the C-code into a multi-rate data flow graph representation by handling the nested loops. The main steps of the method are illustrated by a simple example.

A method for avoiding loops while decomposing the task description graph in system-level synthesis

In system-level synthesis, the graph describing the task may consist of a great number of vertices, thus the design algorithms (e.g. hardware-software partitioning, pipeline synthesis, etc.) may become extremely complicated. This difficulty is relaxed by decomposing the task description graph that is usually unavoidable in system-level synthesis. The decomposing algorithms unite certain vertices of the graph, thus the resulting graph consists of less vertices. However, loops may appear in the decomposed graph, even if the original graph was loop-free, that endangers the efficiency of the design algorithms. We propose an algorithm that generates allowable cuts. We prove that any decomposition made along these cuts always yields a loop-free graph. The method is demonstrated on a simple example. Incorporating optimization criteria in the cut generation is also discussed.

Component-Based Hardware-Software Co-design

The unbelievable growth in the complexity of computer systems poses a difficult challenge on system design. To cope with these problems, new methodologies are needed that allow the reuse of existing designs in a hierarchical manner, and at the same time let the designer work on the highest possible abstraction level. Such reusable building blocks are called components in the software world and IP (intellectual property) blocks in the hardware world. Based on the similarity between these two notions the authors propose a new system-level design methodology, called component-based hardware-software co-design, which allows rapid prototyping and functional simulation of complex hardware-software systems. Moreover, a tool is presented supporting the new design methodology and a case study is shown to demonstrate the applicability of the concepts.