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Peter B. Holmqvist

Nvidia

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Archive | 2008

Multi-class data cache policies

David B. Glasco; Peter B. Holmqvist; George R. Lynch; Patrick R. Marchand; James Roberts

Archive | 2010

EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CACHING

David B. Glasco; Peter B. Holmqvist; George R. Lynch; Patrick R. Marchand; Karan Mehra; James Roberts; Cass W. Everitt; Steven E. Molnar

Archive | 2008

System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy

David B. Glasco; Peter B. Holmqvist; George R. Lynch; Patrick R. Marchand; James Roberts; John H. Edmondson

Archive | 2008

Cache-based control of atomic operations in conjunction with an external ALU block

David B. Glasco; Peter B. Holmqvist; George R. Lynch; Patrick R. Marchand; Karan Mehra; James Roberts

Archive | 2014

Compression Status Bit Cache And Backing Store

David B. Glasco; Peter B. Holmqvist; George R. Lynch; Patrick R. Marchand; Karan Mehra; James Roberts

Archive | 2008

System, method and frame buffer logic for evicting dirty data from a cache using counters and data types

David B. Glasco; Peter B. Holmqvist; George R. Lynch; Patrick R. Marchand; James Roberts; John H. Edmondson

Archive | 2006

Method and apparatus to ensure consistency of depth values computed in different sections of a graphics processor

Stuart F. Oberman; Steven E. Molnar; Alexander L. Minkin; Peter B. Holmqvist

Archive | 2008

Using a data cache array as a DRAM load/store buffer

James Roberts; David B. Glasco; Patrick R. Marchand; Peter B. Holmqvist; George R. Lynch; John H. Edmondson

Archive | 2012

CONTROL MECHANISM FOR FINE-TUNED CACHE TO BACKING-STORE SYNCHRONIZATION

James P. Robertson; Gregory Alan Muthler; Hemayet Hossain; Timothy John Purcell; Karan Mehra; Peter B. Holmqvist; George R. Lynch

Archive | 2011

Class Dependent Clean and Dirty Policy

David B. Glasco; Peter B. Holmqvist; George R. Lynch; Patrick R. Marchand; James Roberts; John H. Edmondson

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