Peter B. K. Kyabaggu

Design and characterisations of double-channel GaAs pHEMT Schottky diodes based on vertically stacked MMICs for a receiver protection limiter

A microwave receiver protection limiter circuit has been designed, fabricated and tested using vertically stacked GaAs MMIC technology. The limiter circuit with a dimension of 2.5 × 1.3 mm2 is formed by using double-channel AlGaAs/InGaAs pseudomorphic HEMT (pHEMT) Schottky diodes integrated with a low-loss V-shaped coplanar waveguide multilayer structure. The electrical parameter characteristics of the pHEMT Schottky diodes are presented including the C–V profile showing the presence of a double channel in the device layer structure. This unique feature can also be seen from the double-peak responses of the electron density as a function of the device layer width, which represent the high electron concentration at two different 2-DEG layers of the structure. An equivalent circuit model of pHEMT Schottky diodes is demonstrated showing good agreement with the measurement results. At zero-bias condition, the devices show high performance in diode detector applications with voltage sensitivities of more than 89 mV μW−1 at 10 GHz and at least 5.4 mV μW−1 at 35 GHz. The measurement results of the limiter circuit demonstrated the blocking of input power signals greater than 20 dBm input power at 3 GHz. To the best of our knowledge this is the first demonstration of the use of pHEMT Schottky diodes in microwave power limiter applications.

3D momentum modeling technique and measurements of CPW compact GaAs multilayer MMICs

New electromagnetic modeling technique using 3D momentum optimization has been developed to accurately model compact multilayer coplanar waveguide (CPW) MMICs. Suitable layout simulation setups are provided which showed good agreements with the measured data. Furthermore, a TOM3 schematic design of a MMIC GaAs pHEMT has been developed and compared with its TOM3 netlist file along with the measured results. The fabricated multilayer MMIC amplifier has also been characterized and compared with the simulation data. In addition, we demonstrate the utilization of the optimized amplifier model in understanding parasitic inductance in the on-wafer measurement.