Peter C. Mills

26.1 A 130mW 20Gb/s half-duplex serial link in 28nm CMOS

As the processing power and clock rate of CPUs and GPUs increase, there is a need for increased I/O bandwidth to enable chip-to-chip communication. I/O pin limitations demand faster links at low power to enable integration of high chip-to-chip bandwidth. However, the channel losses and impedance discontinuities increase at high data rates making it difficult to equalize the channel at low power. In this work, we target reliable, differential, bi-directional links at 20 Gb/s over 6” FR4 PCB trace and flip-chip packages with a total loss budget of 20 dB at Nyquist. In a half-duplex link, one TX and RX are connected on each side and the link direction can be turned around by the controller. A link-turnaround latency of <;10 ns is achieved by placing several key circuits on standby when not in use and by designing fast bias circuits. When fast turnaround is not required, the circuits not in use are powered down permanently and the link is reduced to the simplex case. The top-level transceiver architecture is shown. An LC-VCO-based PLL oscillates at 20 GHz and generates quadrature I/Q clocks at 10 GHz. Both TX and RX use a half-rate architecture to optimize power. The clocks are distributed through an on-chip transmission line to 16 I/O lanes arranged in 2 rows. The links are capable of data rates as low as 14 Gb/s to save power when full bandwidth is not required.